结构化 VHDL 代码中的端口映射 [英] port map in structural VHDL code

问题描述

我有以下用于 VHDL 结构建模的代码.当我尝试编译它 (ghdl -a filename.vhdl) 时，我在下面注释的 4 行中收到此错误:"<=" or ":=" expected 而不是 port

I have the following code for a structural modeling in VHDL. When I try to compile it (ghdl -a filename.vhdl), I get this error in the 4 lines commented below: "<=" or ":=" expected instead of port

顺便说一句，我已经定义了下面代码块之前使用的组件.

BTW, I had already defined the components used before the code block below.

我的代码有什么问题?我是否不允许在进程/if 语句中使用 port map?

What's wrong with my code? Am I not allowed to use port map inside a process/if-statement?

我该怎么做才能解决这个问题?谢谢！

What can I do to fix this? Thanks!

-- Entity Definition
entity jk is
    port(
        CP: in std_logic; -- clock signal
        J : in std_logic; -- J signal
        K : in std_logic; -- K signal
        Q : inout std_logic; -- Q signal
        QN : inout std_logic; -- Q' signal
        reset : in std_logic -- reset signal
    );
end entity jk;

architecture dev1 of jk is

    -- declare the singals that outputs the results of some gates
    signal a, b, internal_q, internal_qn : std_logic;

    -- get each component needed
    component and3 is
        port(o0 : out std_logic; i0, i1, i2: in std_logic);
    end component and3;
    component nor2 is
        port(o0 : out std_logic; i0, i1: in std_logic);
    end component nor2;

begin

    internal_q <= Q;    -- used to show internal Q value
    QN <= not Q;        -- inverse of Q
    internal_qn <= QN;  -- used to show internal QN value

    process is
    begin
        if (reset = '0') then -- asynchronous reset
            Q <= '0';
            internal_qn <= '0';
        elsif rising_edge(CP) then -- on positive clock edge
            -- AND gate outputs
            g0: and3 port map(a, internal_q, K, CP); -- error
            g1: and3 port map(b, internal_qn, J, CP); - error

            -- NOR gate outputs
            g2: nor2 port map(Q, a, internal_qn); -error
            g3: nor2 port map(QN, b, internal_q); -error
        end if;
    end process;

end architecture dev2;

推荐答案

不，不允许在进程内部实例化组件(使用端口映射).

No, you are not allowed to instantiate components (use port maps) inside of a process.

您应该在架构的 begin 语句下方实例化您的组件.将它们适当地连接到那里.您的流程应该驱动所有已注册的逻辑.我实际上在这段代码中根本没有看到任何流程语句的需要.由于您的所有输入都来自您的实体(我假设)，因此您实际上不需要在此文件中执行任何注册逻辑.

You should be instantiating your components below the begin statement of your architecture. Wire them up there appropriately. Your process should drive all of the registered logic. I actually don't see any need for a process statement at all in this code. Since all of your inputs are coming from your entity (I assume) then you really don't need to do any registered logic in this file.

您也可以发布您的实体吗?我看不到信号 J 和 K 以及 CP 和 Q 和 QN 的定义位置.

Can you post your entity as well? I cannot see where signals J and K and CP and Q and QN are being defined.

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