在合成后仿真中得到错误的结果 [英] Getting wrong results in post synthesis simulation

问题描述

我正在VHDL中编写Matrix Transpose的代码，我在行主输入和每个时钟周期输入一个矩阵元素，并以列主格式存储数据，之后我通过列主格式元素发送数据在每个时钟周期到输出的元素.代码如下所示，它在正确模拟，但是后期合成结果不正确，任何人都可以帮助如何合成代码以获得正确的结果

I am writing a code for Matrix Transpose in VHDL i am taking input in row major and one element of matrix per every clock cycle and i store the data in column major format after that i send tha data in coloumn major format element by element every clock cycle to the output . The code is as below it is simulating properly but the post synthesis results are not right can anyone plz help how to synthesize code to get correct results

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity Matrix_Trans_Sysgen is
generic(n: integer :=3);
port (my_clk : in std_logic;
my_ce : in std_logic;
input_matrix : in std_logic_vector(5 downto 0);
output_matrix : out std_logic_vector(5 downto 0)
);
end Matrix_Trans_Sysgen;

architecture Behavioral of Matrix_Trans_Sysgen is

type t1 is array (natural range<>) of std_logic_vector(5 downto 0);

signal a : t1((n*n)-1 downto 0) :=(others => (others =>'0'));

signal output_there : std_logic :='0';

signal x : integer range 0 to 2*n :=0;
signal y : integer range 0 to 2*n :=0;
signal z : integer range 0 to 2*n*n :=0;

begin

----- Process to take all input_matrix into array
process(my_clk,input_matrix,x,y)
begin

if(x < n) then

    if(y < n) then
       if(rising_edge(my_clk)) then 
          a(y*n+x) <= input_matrix;
          y <= y+1;
       end if;
    else
      x<=x+1;
      y<=0;
    end if;
  else
    output_there <= '1';

end if;
end process;


----- Process to send all output elements through port
process(my_clk,z,output_there)
begin

if (output_there = '1') then

    if(z < n*n) then


      if(rising_edge(my_clk)) then


         output_matrix <= a(z);
         z<=z+1;

      end if;

    end if;

end if;

end process;

end Behavioral;

感谢和问候

Teja

推荐答案

使用用于计时进程的常用模板将其重写.也就是说，使用

Rewrite it using the usual template for clocked processes. That is, with

"如果rising_edge(clk)，则... "

在此过程中最远.综合工具会寻找并正确处理此构造.其他形式的过程可能会混淆工具.

outermost in the process. Synthesis tools look for this construct and handle it correctly; other forms of process can confuse the tools.

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