如何在门逻辑仿真中检测振荡? [英] How to detect oscillations in gate logic simulations?

问题描述

我正在用C#编写基于周期的逻辑仿真.我想模拟组合电路和顺序电路.组合电路很简单，但是顺序电路给我带来麻烦.

I'm writing cycle based logic simulation in C#. I want to simulate both combinational and sequential circuits. Combinational circuits are straightforward but sequential circuits give me trouble.

我想检测振荡并显示适当的警告消息.是否有一种简单的方法来检查单个门可以改变其状态多少次，并且仍然使电路保持稳定?

I want to detect oscillations and display appropriate warning message. Is there a simple way to check how many times a single gate can change its state and still leave the circuit stable?

我想到了最小反馈弧集算法"，但这似乎是一个过大的选择.许多桌面应用程序执行此操作的速度很快，所以我怀疑他们正在使用它.

I thought about 'minimum feedback arc set algorithm' but it seems to be an overkill. Many desktop applications does this fast so I doubt they're using it.

我还发现有论文建议使用三元逻辑(0、1，未知)和拆分算法，该算法分为两部分-初始化电路，进行实际计算-但它说的是如果算法A没有，终止电路会产生振荡，这使我一无所获，因为无法停止时钟周期并警告用户.

I also found paper advising the use of ternary logic (0, 1, unknown), and splitting algorithm in two parts - one initializing the circuit and one doing actual computations - but it was saying something like 'if algorithm A does not terminate the circuit has oscillations' which gives me nothing since there is no way to stop the clock cycle and warn the user.

有什么想法，例如"Logisim"或数字作品"之类的应用如何检测振荡?

Any ideas how applications like "Logisim" or "digital works" detect oscillations ?

推荐答案

Verilator 是一种逻辑模拟器，其工作原理是将可综合的Verilog编译为C代码.

Verilator is a logic simulator that works by compiling synthesizable Verilog into C code.

它试图构造一个可以保证稳定的逻辑顺序，但是如果失败，它将发出一些UNOPT和UNOPTFLAT警告，并简单地重复模拟多次，直到没有任何变化为止.

It tries to construct an order of logic that will be guaranteed to be stable, but if it fails it emits some UNOPT and UNOPTFLAT warnings and simply repeats the simulation a number of times until nothing changes.

默认情况下，在报告收敛失败之前会使用100轮，但是可以使用参数收敛极限.

By default, 100 rounds are used before it reports a failure to converge, but this can be changed using argument converge-limit.

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