为什么CPSR不是存入银行注册？ [英] Why is CPSR not a banked register?

问题描述

在ARM的SPSR是分组寄存器即在模式每次更改后，CPSR被复制到SPSR，模式返回后，将SPSR复制回CPSR。为什么CPSR不是直接存入银行？好像有每模式改变两个额外的指令（复制到SPSR，复制到CPSR）

解决方案

手动模式的变化并不在 ARM 的效率目标。通常情况下，的手动模式的更改仅完成设置栈等在启动或初始化时间。

的 CPSR 是有效的副本。为什么我们有库存的 LR 注册，但不是当前 PC ？在 SPSR 为篇章 CPSR 为不同的模式;就像开户 LR 是 PC 为不同的模式。在银行是这样的异常状态可以是透明的。在 SPSR 被存入银行作为中止的可在任何模式下发生的中断或的数据;我们需要保存它，使我们正确的栈执行。正常的非银行的用户模式从来没有与其它模式栈。的模式的更改会自动在的异常情况的

完成

模式寄存器设置，以使的异常处理的非常有效和灵活。的手动模式的更改不会非常方便，因为它们通常不使用。您可以复制任何开户注册到一个未开户切换模式，使国家能够在两者之间传输之前之一;当的系统的用于所有的异常处理的模式，这是常见的。在这种情况下，寄存器通常存储到一个<青霉>任务上下文块的内核和有<青霉>存储器存储的这种意愿管道这不是一个效率的问题。

In ARM, the SPSR is a banked register i.e. after every change in mode, CPSR is copied into the SPSR, and after the mode returns, the SPSR is copied back to CPSR. Why is the CPSR not banked directly? It seems like there are two additional instructions with every mode change (copy into spsr, copy into cpsr)

解决方案

Manual mode changes are not an efficiency goal on the ARM. Typically, manual mode changes are only done to setup stacks, etc at boot or initialization time.

The cpsr is the active copy. Why do we have a banked lr register but not the current pc? The spsr is a banked cpsr for a different mode; just like the banked lr is the pc for a different mode. The banking is so that the exception state can be transparent. The spsr is banked as an interrupt or data abort may occur in any mode; we need to save it so that we stack execution correctly. The normal unbanked user mode never stacks with another mode. mode changes are done automatically in exception conditions.

The mode registers are setup to make exception handling very efficient and flexible. Manual mode changes are not highly convenient as they are not normally used. You can copy any banked register to an un-banked one before switching modes so that the state can be transferred between the two; this is common when system mode is used for all exception handling. In this case, the registers are often stored to a task context block by the kernel and this is not an efficiency issue as there are memory stores that will pipeline.

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