为什么 CPSR 不是银行寄存器? [英] Why is CPSR not a banked register?

问题描述

在 ARM 中，SPSR 是一个分组寄存器，即每次模式更改后，CPSR 都会复制到 SPSR，模式返回后，SPSR 会复制回 CPSR.为什么 CPSR 不直接存入银行?每次模式更改似乎都有两条额外的指令(复制到spsr，复制到cpsr)

In ARM, the SPSR is a banked register i.e. after every change in mode, CPSR is copied into the SPSR, and after the mode returns, the SPSR is copied back to CPSR. Why is the CPSR not banked directly? It seems like there are two additional instructions with every mode change (copy into spsr, copy into cpsr)

推荐答案

手动模式更改不是 ARM 的效率目标.通常，手动模式更改仅用于在启动或初始化时设置堆栈等.

Manual mode changes are not an efficiency goal on the ARM. Typically, manual mode changes are only done to setup stacks, etc at boot or initialization time.

cpsr 是活动 副本.为什么我们有一个存储的 lr 寄存器而不是当前的 pc?spsr 是一个 banked cpsr 用于不同的模式；就像银行的 lr 是不同模式的 pc 一样.banking 使得异常状态可以是透明的.spsr 被存储为 interrupt 或 data abort 可能在任何模式下发生；我们需要保存它以便我们 stack 正确执行.普通的unbanked 用户模式永远不会与其他模式叠加.模式变化是在异常情况中自动完成的.

The cpsr is the active copy. Why do we have a banked lr register but not the current pc? The spsr is a banked cpsr for a different mode; just like the banked lr is the pc for a different mode. The banking is so that the exception state can be transparent. The spsr is banked as an interrupt or data abort may occur in any mode; we need to save it so that we stack execution correctly. The normal unbanked user mode never stacks with another mode. mode changes are done automatically in exception conditions.

设置模式寄存器以使异常处理非常高效和灵活.手动模式更改不是很方便，因为它们通常不使用.您可以在切换模式之前将任何已存储的寄存器复制到未存储的寄存器，以便在两者之间转移状态；这在 system 模式用于所有异常处理 时很常见.在这种情况下，寄存器通常由内核存储到任务上下文块，这不是效率问题，因为存在将流水线的内存存储.

The mode registers are setup to make exception handling very efficient and flexible. Manual mode changes are not highly convenient as they are not normally used. You can copy any banked register to an un-banked one before switching modes so that the state can be transferred between the two; this is common when system mode is used for all exception handling. In this case, the registers are often stored to a task context block by the kernel and this is not an efficiency issue as there are memory stores that will pipeline.

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