什么是MRC命令的附加协处理器寄存器的功能？ [英] What is the function of the additional coprocessor register of the MRC command?

问题描述

从ARM报价 MRC 文件，

  MRC {2}＆LT; C＆GT;＆LT; Q＆GT; ＆LT;协处理器＆gt;中＃＆LT; OPC1＆GT中，＆lt;保留时间＆GT中，＆lt; CR n的＆gt;中＆LT; CRM和GT; {，＃＆LT;＆OPC2 GT;}
 

  
  

其中：

  
  

2 如果指定，选择编码T2 / A2。如果省略，选择编码T1 / A1。

  
  

＆LT; C＆GT;＆LT; Q＆GT; 见网页上A8-7标准汇编语法领域。一个ARM指令MRC2必须是无条件的。

  
  

＆LT;＆协处理器GT; 协处理器的名称。标准的通用处理器名称为P0，P1，...，P15。

  
  

＆LT; OPC1方式＆gt; 的范围是特定的协处理器运算code 0〜7

  
  

＆LT;保留时间＆GT; 是目标ARM内核寄存器。该寄存器可以R0-R14或APSR_nzcv。最后形式写入所传送的值的N，Z，C和V条件标志的位[31:28]和由编码的保留时间字段设置为0b1111指定。在pre-UAL汇编程序语法，PC写的，而不是APSR_nzcv选择这种形式。

  
  

＆LT; CR n的方式＆gt; 是包含第一个操作数的协处理器寄存器

  
  

＆LT客户关系管理方式＆gt; 是一个额外的源或目的协处理器寄存器

  
  

＆LT; OPC2＆GT; 是一个特定于协处理器的运算code范围为0〜7。如果省略，＆LT; OPC2＆GT; 假定为0

如果 MRC 是为了一个协处理器寄存器的内容复制到一个单一的ARM寄存器，什么是 CRm上？另外，我不太清楚什么是运算code 的原因要么是，但那是较小的相关性。

解决方案

user786653可能击中头部与该链接的钉子。

我知道老FPU的FPA，使用协处理器接口，如果你去code中的FPA浮点指令我想你会发现，他们排队与通用协处理器运算code模式（ MRC / MCR）。

我点我不会得到在该指令激动了各个领域，有些领域可能不要至于协处理器而言问津。 ARM处理器和汇编程序不必然知道你迷上了什么，这是把位模式为机器指令的通用方法。你需要专注于你所谈论的具体协处理器，其TRM专门与该逻辑匹配的版本号（如果可能的话，如果从ARM）假设协处理器的TRM是胳膊，如果是别人的协处理器，然后用它们的文档。字段被用于通过在协处理器的每个操作都希望定义不够好。如果他们不谈论什么的一个字段意味着我会假设它不关心。剪切和粘贴手册，如果有他们的MRC / MCR线，如果不是谷歌周围，也许找一些已经很好用code和剪切和粘贴图案和/或尝试不同的东西未定义领域，看看是否改变操作。

一般地虽然MRC / MCR领域的定义不是一成不变的，供应商可以创建一个协处理器，做任何他们想做的那些领域。像FPA也许去，至于改变汇编器/反汇编器来创建一个新的扩展指令集。 ARM内核可能关心的ARM寄存器本身，如果没有为协处理器接口本身我不会感到惊讶，一个TRM如果一个协处理器读有一个控制线，告诉手臂或不修改指定ARM寄存器根据协处理器驾驶该信号。

Quoting from the ARM MRC documentation,

MRC{2}<c><q> <coproc>, #<opc1>, <Rt>, <CRn>, <CRm>{, #<opc2>}

where:

2 If specified, selects encoding T2 / A2. If omitted, selects encoding T1 / A1.

<c><q> See Standard assembler syntax fields on page A8-7. An ARM MRC2 instruction must be unconditional.

<coproc> The name of the coprocessor. The standard generic coprocessor names are p0, p1, …, p15.

<opc1> Is a coprocessor-specific opcode in the range 0 to 7.

<Rt> Is the destination ARM core register. This register can be R0-R14 or APSR_nzcv. The last form writes bits [31:28] of the transferred value to the N, Z, C and V condition flags and is specified by setting the Rt field of the encoding to 0b1111. In pre-UAL assembler syntax, PC was written instead of APSR_nzcv to select this form.

<CRn> Is the coprocessor register that contains the first operand.

<CRm> Is an additional source or destination coprocessor register.

<opc2> Is a coprocessor-specific opcode in the range 0 to 7. If omitted, <opc2> is assumed to be 0.

If MRC is meant to copy contents of a single coprocessor register into a single ARM register, what is the reason for CRm? Also, I'm not quite sure what the reason for an opcode is either, but that's of lesser relevance.

解决方案

user786653 may have hit the nail on the head with that link.

I know the old fpu, the fpa, used the coprocessor interface and if you decode the fpa floating point instructions I think you will find they line up with the opcode pattern for a generic coprocessor (mrc/mcr).

My point is I wouldnt get worked up over every field in that instruction, some field are likely dont cares as far as the coprocessor is concerned. The ARM processor and assembler dont necessarily know what you have hooked up and this is a generic way to put bit patterns into a machine instruction. You need to focus on the specific coprocessor you are talking to, its TRM specifically the TRM with matching version numbers for that logic (if possible, if from ARM) assuming that coprocessor is from arm, if it is someone elses coprocessor then use their documentation. the fields being used by each operation in that coprocessor are hopefully defined well enough. If they dont talk about what one of the fields means I would assume it a dont care. Cut and paste their mrc/mcr line in the manual if there, if not google around maybe find some already well used code and cut and paste that pattern and/or try different things for the undefined fields and see if that changes the operation.

Generically though the mrc/mcr field definitions are not set in stone, a vendor can create a coprocessor and do whatever they want with those fields. Like the FPA perhaps going so far as to change the assembler/disassembler to create a new extension to the instruction set. the arm core may care about the ARM register itself, If there is a TRM for the coprocessor interface itself I wouldnt be surprised if a coprocessor read has a control line that tells the arm to or not to modify the specified arm register based on the coprocessor driving that signal.

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