处理 SystemVerilog 包中的参数化 [英] Handling parameterization in SystemVerilog packages

问题描述

SystemVerilog 添加了包来为公共代码片段(函数、类型、常量等)提供命名空间.但是由于包没有被实例化，它们不能被参数化，所以处理参数化的成员是有问题的.在实践中，我发现这非常有限，因为我的自定义类型经常有一些参数来指示字段宽度等.

SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parameterized, so dealing with parameterized members is problematic. In practice I have found this pretty limiting since very often my custom types have some parameters dictating field widths etc.

我通常通过使用具有默认值的参数来处理这个问题，并且只是理解我需要回去更改某些应用程序的包源代码，这对我来说似乎是非常错误的.但我还没有找到一种方法来更干净地处理这个问题.例如:

I generally deal with this by using parameters with default values and just understanding that I will need to go back change the package source code for some applications, which seems very wrong to me. But i have yet to find a way to handle this more cleanly. For example:

package my_pkg;
    parameter ADDR_MSB = 7;
    parameter DATA_MSB = 31;

    typedef struct {
        logic [ADDR_MSB:0] address;
        logic [DATA_MSB:0] data;
    } simple_struct_t;

endpackage

有没有人找到一种更简洁的方法来处理这个问题?我很想听听它，因为我认为包是 SV 的一个非常强大的补充，可以实现更安全的代码重用，但这种限制非常严重.

Has anyone found a cleaner way of dealing with this? I'd love to hear about it since I think packages are a very powerful addition to SV enabling safer code reuse, but this limitation is pretty severe.

推荐答案

我有几个想法.首先，我倾向于使用类而不是结构来建模我的数据.类可以参数化、动态分配、随机化、包含覆盖组等.我只在需要打包结构时才使用结构.打包结构非常棒，因为您可以像常规向量一样分配给它们，然后使用命名字段访问数据.非常好.:)

I have a couple of thoughts. First, I would lean towards modeling my data using classes instead of structs. Classes can be parameterized, dynamically allocated, randomized, contain covergroups, etc. I only use structs when I want a packed struct. Packed structs are wonderful because you can assign to them like a regular vector and then access the data using the named fields. Very nice. :)

第二，即使可以重新定义包参数，模拟中也只有一个包的实例"；不能像模块或类那样有多个具有不同参数值的特化.所以在我看来，取消参数并使用宏是一个可行的解决方案.虽然我不喜欢使用宏，但这将允许您在不更改源代码的情况下使用新值重新编译.

Second, even if it were possible to redefine package parameters, there is only one "instance" of a package in a simulation; there can't be multiple specializations with different parameter values like there can be for modules or classes. So it seems to me that doing away with the parameter and using a macro instead is a workable solution. Although I don't like using macros, that would allow you to recompile with new values without changing the source code.

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