在模块实例化中输入对另一个模块的引用?(SystemVerilog) [英] Input a reference to another module in a module instantiation? (SystemVerilog)

问题描述

我有专门的测试平台模块，用于在我的测试平台中打印/跟踪有关 DUT 的信息.我想避免将所有有趣的(内部)信号连接到 tb 模块中.

I have dedicated testbench module for printing/tracing information about the DUT in my testbench. I would like to avoid having to wire all the interesting (internal) signals down into the tb module.

举个例子，假设我的 DUT 中有一个内部信号 a.如何在 printer.sv 中访问它而不必创建匹配的输入?草图:

As an example let's say I have an internal signal a in my DUT. How can I access it in printer.sv without having to create a matching input? Sketch:

/---- TB.sv -----------------------------------------\
|                                                    |
|   /--dut.sv--\       /--printer.sv-------------\   |
|   | wire a;  |   ->  | always @(posedge clk)   |   |
|   |          |       | $display("a is %d", a); |   |
|   \----------/       \-------------------------/   |
|                                                    |
\----------------------------------------------------/

我一直在查看 bind 关键字，看看它是否对我有帮助，但我不明白.

I have been looking at the bind keyword to see if it could help me, but I don't understand it.

printer.vs 需要的信号数量很大，所以我真的很想避免必须将所有内容都声明为输入，这很乏味.

The number of signals needed by the printer.vs is large, so I would really like to avoid having to declare everything as inputs, it's very tedious.

是否有某种方法可以将分层引用传递给实例化的 dut 模块?

Is there some way to pass in a hierarchical reference to the instantiated dut module?

推荐答案

可以在绑定的打印机模块中使用向上引用.

You can use an upwards reference in the bound printer module.

module DUT(input clk);     
     wire a;
     function void hello;
       $display("Hello from %m");
     endfunction
      
endmodule
    
module printer(input clk);
      always @(posedge clk)
        $display("a is %d", DUT.a);
      initial DUT.hello;
endmodule
    
module TB;
      reg clock;
      DUT d1(clock);
      DUT d2(clock);
      
      bind DUT printer p(clk);
      
endmodule

并不是说向上的名称引用是 Verilog 独立于 bind 的一个特性.绑定功能的工作原理就像您在 DUT 中编写实例一样.这与您可以使用顶级模块名称作为引用开头的原因相同.

Not that upwards name referencing is a feature of Verilog independent of bind. The bind feature works exactly as if you had written the instance inside the DUT. It the same reason you can use the top-level module name as the beginning of a reference.

module DUT(input clk);     
     wire a;
     function void hello;
       $display("Hello from %m");
     endfunction

      printer p(clk);  // what bind is actually doing

      
endmodule
    
module printer(input clk);
      always @(posedge clk)
        $display("a is %d", DUT.a);
      initial DUT.hello;
endmodule
    
module TB;
      reg clock;
      DUT d1(clock);
      DUT d2(clock);      
endmodule

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