如何在 VLSI 设计中物理实现寄存器的后门访问? [英] How is backdoor access for registers, physically implemented in a VLSI design?

问题描述

可合成寄存器通常可以使用使用地址 & 的访问技术来验证.数据总线(这些总线是硅芯片上实际硬件的很大一部分).但是这种传统的访问技术消耗的时间是有限的.

Synthesizable register(s) can conventionally be verified using access technique that use address & data buses (these buses are very much part of the actual hardware present on the silicon chip). But this conventional access technique consumes finite time.

带有 UVM 的寄存器抽象层 (RAL) 是验证设计中 RTL 寄存器的非常有效的方法.这种方法的主要特征之一是'后门访问'，凭借它可以访问(即读取或写入)中的任何 RTL 寄存器零模拟时间.后门访问机制使用分层 HDL 路径来实现.

Register Abstraction Layer (RAL) with UVM is a very efficient way of verifying RTL registers in your design. One of the key features of this methodology is 'backdoor access', by virtue of which one can access (i.e. read from or write into) any RTL register(s) in zero simulation time. The backdoor access mechanism uses hierarchical HDL paths to do so.

问题是硅片上的哪些物理条件使零时间访问成为可能?

The question is what physical provisions on the silicon makes this, access-in-zero-time, possible?

推荐答案

UVM 中的寄存器抽象层使用仅在模拟期间可用的技术提供对寄存器的后门访问.这可能是通过综合工具不允许的分层引用，或者使用像 DPI 这样的工具编程接口.所以后门在这里指的是仿真工具修改设计状态的能力.

The Register Abstraction Layer in the UVM provides backdoor access to registers using techniques only available during simulation. This could be through hierarchical references not allowed by synthesis tools, or using a tool programming interface like the the DPI. So backdoor here refers to a simulation tool's ability to modify the state of the design.

当然，后门在设计中可以绕过用于访问寄存器的正常硬件协议，但这是设计的一个功能方面，永远不会在 0 次发生.扫描链是后门硬件访问的一个例子.

There is, of course, backdoors in design that circumvent the normal hardware protocol for accessing registers, but that is a functional aspect of the design and would never occur in 0 time. A scan chain would be an example of backdoor hardware access.

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