行为建模不是 testbench.test 中的有效 l 值 [英] Behavioral Modeling is not a valid l-value in testbench.test
问题描述
我正在尝试使用两个二进制输入 A 和 B 来获得二进制输出,即 F 就像下面的真值表一样,但它一直说:
main.v:36: 错误:F3 不是 testbench.test 中的有效左值main.v:27:: F3 在这里被声明为 wire.
这是我的模型的真值表.
A1 A0 B1 B0|F3 F2 F1 F00 0 0 0 |0 0 0 00 0 0 1 |0 0 0 00 0 1 0 |0 0 0 00 0 1 1 |0 0 0 00 1 0 0 |0 0 0 00 1 0 1 |0 0 0 10 1 1 0 |0 0 1 00 1 1 1 |0 0 1 11 0 0 0 |0 0 0 01 0 0 1 |0 0 1 01 0 1 0 |0 1 0 01 0 1 1 |0 1 1 01 1 0 0 |0 0 0 01 1 0 1 |0 0 1 11 1 1 0 |0 1 1 01 1 1 1 |1 0 0 1
我的 icarus Verilog 代码在这里:
<预><代码>模块乘法(A1,A0,B1,B0,F3,F2,F1,F0);输入 A1,A0,B1,B0;输出 F3,F2,F1,F0;总是@(A1或A0或B1或B0)开始if({A1,A0}*{B1,B0})开始{F3,F2,F1,F0}=4'b0001;{F3,F2,F1,F0}=4'b0010;{F3,F2,F1,F0}=4'b0011;{F3,F2,F1,F0}=4'b0010;{F3,F2,F1,F0}=4'b0100;{F3,F2,F1,F0}=4'b0110;{F3,F2,F1,F0}=4'b1001;结尾结尾结束模块模块测试台;reg [1:0] A,B;//这些就像开关线 F3,F2,F1,F0;//像一个 LED//测试verilog模型乘法测试(A[1],A[0],B[1],B[0],F3,F2,F1,F0);//生成输入最初的开始//喜欢{//显示电路的响应//对于每个输入组合$display("-------------------------------------------------------");$display(两个 2 位二进制输入的乘法等于 4 位二进制输出");$display("-------------------------------------------------------");$display(时间\tA\tB\tF3\tF2\tF1,\tF0");$display("-------------------------------------------------------");$monitor("%g\t%d\t%d\t%d\t%d\t%d",$time,A,B,F3,F2,F1,F0);#15 $finish;结尾初始开始 A = 0;乙 = 0;结尾总是 #1 B[0] = ~B[0];总是#2 B[1] = ~B[1];总是#4 A[0] = ~A[0];总是#8 A[1] = ~A[1];永远#3$display("-------------------------------------------------------");结束模块由于您在 always
块内对 F3
进行赋值,因此必须将其声明为 注册
.F2、F1、F0 也是一样:
module Multiply(A1,A0,B1,B0,F3,F2,F1,F0);输入 A1,A0,B1,B0;输出 F3,F2,F1,F0;注册 F3,F2,F1,F0;
这修复了编译错误并允许您的模拟运行.但是,我认为 Verilog 代码与真值表不匹配.
编写真值表的常用方法是使用 case
语句:
module Multiply(A1,A0,B1,B0,F3,F2,F1,F0);输入 A1,A0,B1,B0;输出 F3,F2,F1,F0;注册 F3,F2,F1,F0;总是@* 开始案例 ({A1,A0,B1,B0})4'b0101 : {F3,F2,F1,F0}=4'b0001;4'b0110 : {F3,F2,F1,F0}=4'b0010;4'b0111 : {F3,F2,F1,F0}=4'b0011;4'b1001 : {F3,F2,F1,F0}=4'b0010;4'b1010 : {F3,F2,F1,F0}=4'b0100;4'b1011, 4'b1110 : {F3,F2,F1,F0}=4'b0110;4'b1111 : {F3,F2,F1,F0}=4'b1001;默认:{F3,F2,F1,F0}=4'b0000;尾箱结尾结束模块
I am trying to use two binary inputs A and B to get the binary output which is the F just like the truth table below, but it keeps saying:
main.v:36: error: F3 is not a valid l-value in testbench.test
main.v:27: : F3 is declared here as wire.
This is the truth table for my model.
A1 A0 B1 B0| F3 F2 F1 F0
0 0 0 0 | 0 0 0 0
0 0 0 1 | 0 0 0 0
0 0 1 0 | 0 0 0 0
0 0 1 1 | 0 0 0 0
0 1 0 0 | 0 0 0 0
0 1 0 1 | 0 0 0 1
0 1 1 0 | 0 0 1 0
0 1 1 1 | 0 0 1 1
1 0 0 0 | 0 0 0 0
1 0 0 1 | 0 0 1 0
1 0 1 0 | 0 1 0 0
1 0 1 1 | 0 1 1 0
1 1 0 0 | 0 0 0 0
1 1 0 1 | 0 0 1 1
1 1 1 0 | 0 1 1 0
1 1 1 1 | 1 0 0 1
My icarus Verilog code is here:
module Multiply(A1,A0,B1,B0,F3,F2,F1,F0);
input A1,A0,B1,B0;
output F3,F2,F1,F0;
always@(A1 or A0 or B1 or B0)
begin
if({A1,A0}*{B1,B0})
begin
{F3,F2,F1,F0}=4'b0001;
{F3,F2,F1,F0}=4'b0010;
{F3,F2,F1,F0}=4'b0011;
{F3,F2,F1,F0}=4'b0010;
{F3,F2,F1,F0}=4'b0100;
{F3,F2,F1,F0}=4'b0110;
{F3,F2,F1,F0}=4'b1001;
end
end
endmodule
module testbench;
reg [1:0] A,B; // these are like switches
wire F3,F2,F1,F0; // like an LED
//test the verilog model
Multiply test(A[1],A[0],B[1],B[0],F3,F2,F1,F0);
//Generate inputs
initial
begin//like {
//display the response of the circuit
//for every input combination
$display("--------------------------------------------------------");
$display("Multiplication of Two 2-Binary Inputs equal to 4-bit binary output");
$display("--------------------------------------------------------");
$display("Time\tA\tB\tF3\tF2\tF1,\tF0");
$display("--------------------------------------------------------");
$monitor("%g\t%d\t%d\t%d\t%d\t%d",$time,A,B,F3,F2,F1,F0);
#15 $finish;
end
initial begin A = 0; B = 0; end
always #1 B[0] = ~B[0];
always #2 B[1] = ~B[1];
always #4 A[0] = ~A[0];
always #8 A[1] = ~A[1];
always #3
$display("--------------------------------------------------------");
endmodule
Since you make assignments to F3
within an always
block, you must declare it as reg
. The same is true for F2, F1, F0:
module Multiply(A1,A0,B1,B0,F3,F2,F1,F0);
input A1,A0,B1,B0;
output F3,F2,F1,F0;
reg F3,F2,F1,F0;
That fixes the compile error and allows your simulation to run. However, I don't think that Verilog code matches the truth table.
A common way to code a truth table is to use a case
statement:
module Multiply(A1,A0,B1,B0,F3,F2,F1,F0);
input A1,A0,B1,B0;
output F3,F2,F1,F0;
reg F3,F2,F1,F0;
always @* begin
case ({A1,A0,B1,B0})
4'b0101 : {F3,F2,F1,F0}=4'b0001;
4'b0110 : {F3,F2,F1,F0}=4'b0010;
4'b0111 : {F3,F2,F1,F0}=4'b0011;
4'b1001 : {F3,F2,F1,F0}=4'b0010;
4'b1010 : {F3,F2,F1,F0}=4'b0100;
4'b1011, 4'b1110 : {F3,F2,F1,F0}=4'b0110;
4'b1111 : {F3,F2,F1,F0}=4'b1001;
default : {F3,F2,F1,F0}=4'b0000;
endcase
end
endmodule
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