Verilog 测试台时钟 [英] Verilog Testbench Clock

问题描述

我已经尝试了多种方法，我现在有点绝望.我试图在我的测试台中制作这个时钟，问题是在模拟中它不起作用或者我的模拟似乎冻结了.我知道它必须是时钟.

I have tried this multiple ways, I am a bit desperate now. I have tried to make this clock in my testbench the problem is in simulation it doesn't work or my simulation seems to freeze. I know it has to be the clock.

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
    end
end
initial begin 
    reset = 0; 
    #15 L = 0; R = 0; H = 0;        
    #20 L = 0; R = 0; H = 1;
    #25 L = 0; R = 1; H = 0;
    #30 L = 0; R = 1; H = 1;
    #35 L = 1; R = 0; H = 0;
    #45 L = 1; R = 0; H = 1;
    #50 L = 1; R = 1; H = 0;
    #55 L = 1; R = 1; H = 1;

    reset = 1; 
    #60 L = 0; R = 0; H = 0;        
    #65 L = 0; R = 0; H = 1;
    #70 L = 0; R = 1; H = 0;
    #75 L = 0; R = 1; H = 1;
    #80 L = 1; R = 0; H = 0;
    #85 L = 1; R = 0; H = 1;
    #90 L = 1; R = 1; H = 0;
    #95 L = 1; R = 1; H = 1;
    $stop ; 
 end 

结束模块

推荐答案

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
 end end

尝试将 clk=0 移动到永久循环上方.您不是每 #10 次切换时钟，而是每 #10 个单位将时钟重置为 0，然后立即切换.我认为这在某些情况下仍然可行，但这可能不是您打算做的.

Try moving clk=0 above the forever loop. Instead of toggling the clock every #10 you're resetting the clock to 0 every #10 units, and then toggling it instantly. I think that still might work in some cases, but it's probably not what you intended to do.

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