Verilog 错误:赋值左侧的对象必须具有可变数据类型 [英] Verilog Error: Object on left-hand side of assignment must have a variable data type
问题描述
我正在尝试在 Verilog 中编写一个顶级模块，只要传感器读取的值低于特定数字，该模块就会打开水阀.
I'm trying to write a top-level module in Verilog that will open a water valve whenever a sensor reads values below a certain number.
这是我的代码:
module ProjectDSD(alteraClock, sensorInput, openValve);
input sensorInput, alteraClock;
output openValve;
always @(sensorInput)
begin
if(sensorInput < 100) //sensor value to irrigate at
begin
openValve <= 1; //here
end
else
begin
openValve <= 0; //here
end
end
endmodule
我收到一条错误消息:
赋值左侧的对象openValve"必须具有可变数据类型
Object "openValve" on left-hand side of assignment must have a variable data type
我错过了什么?另外，我可以在 Altera DE2-155 板上使用哪些引脚来输出只有 1 和 0 的数字信号，以便阀门打开/关闭?
What am I missing? Also, which pins can I use on an Altera DE2-155 board to output a digital signal of only 1's and 0's for the the valve to open/close?
推荐答案
s/output openValve/output reg openValve/
s/output openValve/output reg openValve/
输出默认为wire；你需要一个 reg.另请参阅这个问题.
Outputs default to wire; you need a reg. See also this question.
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