Verilog:分层设计中的初始化 [英] Verilog: initialization in hierarchical design

问题描述

我有一些关于 reg 初始化的问题.

I have some questions about reg initialization.

1. 我可以在设计中放入初始块吗?这是一个好方法吗?
2. 如何在我的底部设计中初始化 regs?我是否需要在每个级别创建端口并从上到下给出初始值?对于每次模拟，初始值都不同.

推荐答案

第 1 点:
我们最近在电子论坛上讨论了初步声明.

Point 1:
We recently had a discussion about initial statements on the Electronics forum.

• 测试台上的初始语句是正常的.事实上，如果没有初始语句，编写测试代码会变得更加困难.
• 初始语句在 ASIC、CPLD 或硬编程 FPGA 中是不可能的.
• 您可以在大多数基于 RAM 的 FPGA 中使用初始语句，其中 FPGA 加载后状态有效.但是，如果您有一个不会恢复初始状态的重置"引脚或命令.因此，此类复位后的 FPGA 条件很可能与您的启动状态不同，因此您的设计可能无法正常工作.
• 在某些情况下，实际可合成模块中的初始状态是允许甚至强制模块工作的.请参阅下面的示例.

• Initial statements in test benches are normal. In fact without initial statements it becomes a lot more difficult to write test code.
• Initial statements are not possible in ASICs, CPLDs or hard programmed FPGAs.
• You can use initial statements in a most RAM based FPGAs where the state is valid after the FPGA is loaded. However if you would have a 'reset' pin or command that would not restore the initial state. As such, the FPGA condition after such a reset could well be different from your start-up state and thus your design might not work correctly.
• There are some cases where an initial state in an actual synthesize-able module is allowed or even mandatory for the module to work. See examples below.

示例 1:您有一个除以二的寄存器，没有复位编码为:

Example 1: You have a divide by two register without reset coded as:

divide_by_two <=  ~divide_by_two;
or 
divide_by_two <=  not(divide_by_two);

在模拟中将始终保持X"，但实际上它将以 0 或 1 条件开始，然后在两者之间切换.要解决模拟中的X"，您需要设置一个初始条件.如果初始条件为1"或0"，您的代码应该独立工作.

In simulation that will always remain 'X' but in reality it will start in a 0 or 1 conditions and then toggle between the two. To work around the 'X' in simulation you have the set an initial condition. Your code should work independent if the initial condition is '1' or '0'.

示例 2:您有一个除以四的寄存器，没有复位编码为:

Example 2: You have a divide by four register without reset coded as:

divide_by_four[1:0] <= {divide_by_four[0],~divide_by_four[1]};
or
divide_by_four[1:0] <= divide_by_four[0] & not(divide_by_four[1]);

之所以允许这样做，是因为在操作过程中，两个寄存器会经历四种可能状态中的每一种:00、01、11、10.无论从四个状态中的哪一个开始，顺序始终是重复.再次在模拟中解决XX"问题，您需要设置一个初始条件.如果初始条件为 00、01、10 或 11，您的代码应该独立工作.

The reason why this is allowed is that during operation the two registers go through every of the four possible states: 00, 01, 11, 10. It does not matter in which of the four it starts, the sequence will always be repeated. Again to work around the 'XX' in simulation you have the set an initial condition. Your code should work independent if the initial condition is 00, 01, 10 or 11.

很多设计师认为，除了上面的例子，在合成代码中使用初始语句是危险的，最好避免它们.

A lot of designers feel that, apart for examples like above, the use of initial statements in synthesized code is dangerous and it is better to avoid them.

第 2 点:
您可以使用带有适当 HDL 代码的重置"信号来设置启动条件，而不是初始语句.复位到每个有寄存器的模块是正常的.

Point 2:
Instead of initial statements you can use a 'reset' signal with the appropriate HDL code to set the start condition. It is normal for the reset to go to every module which has registers.

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