Verilog D-Flip-Flop 在异步复位后不重新锁存 [英] Verilog D-Flip-Flop not re-latching after asynchronous reset

问题描述

我有一个带异步复位和使能的触发器.这是我的代码:

I have a flip-flop with an asynchronous reset and an enable. Here is my code:

module DFF_aSR(in, enable, clock, reset, out);
input in, enable, clock, reset;
output out;
reg out;

always @ (posedge clock or posedge reset) begin
    if (reset) begin
        out <= 1'b0;
    end 
    else if (enable) begin
        out <= in;
    end 
end
endmodule

但这是我得到的波形，显示复位后没有发生再锁存，为什么会这样?

But here is my resulting waveform, which shows that the relatch is not happening after the reset, why is this so?

推荐答案

如果/当时钟上升沿出现且数据 stable 为高电平并复位 stable 低.我看到的唯一这样的边缘是在第一个复位脉冲之前.如果您希望锁存器在例如时间 110ns，您应该确保重置输入在此之前变低.如果您的意图是复位应由边沿触发而不是电平触发，则您可能需要使用一对触发器，一个由时钟触发，另一个由复位触发，接线使第一个的 D 输出连接到 Q 的第二个，第二个的 D 连接到第一个的/Q.将锁存器的输出馈入异或门将产生一个信号，该信号将指示哪个信号具有最近的上升沿(警告:同时上升沿可能会触发亚稳态).然后可以通过将锁存数据与 XOR 的输出进行与"运算以及可能的一些危险避免门来形成您似乎想要的信号.

The latch output should go high if/when a rising clock edge occurs with data stable high and reset stable low. The only such edge I see is before the first reset pulse. If you wish for the latch to grab a signal at e.g. time 110ns, you should ensure that the reset input goes low prior to that. If your intention is that reset should be edge-triggered rather than level triggered, you may need to use a pair of flops, one triggered by clock and the other by reset, wired such that the D output of the first connects to Q of the second, and D of the second connects to /Q of the first. Feeding the outputs of the latches into an XOR gate will yield a signal that will indicate which signal had the most recent rising edge (warning: simultaneous rising edges may trigger metastability). The signal you seem to want could then be formed by taking the "AND" of the latched data with the output of the XOR, along with possibly some hazard-avoidance gates.

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