VHDL，时钟进程可以引入锁存器吗? [英] VHDL, Can a clocked process introduce latches?

问题描述

例如在非时钟过程中，必须在每种情况下设置所有信号以防止实现锁存.但这也是计时过程中的问题吗?我一直认为情况并非如此，但我的一个朋友告诉我，我必须在所有情况下设置所有信号，以防止合成即使在这里也引入锁存器.

For example in an unclocked process, all signals have to be set in every case to prevent latches from being implemented. But is this also the matter in a clocked process? I keep thinking this is not the case, but a friend of mine tells me I have to set all signals in all cases to prevent the synthesis from introducing latches even here.

推荐答案

正确实现的时钟进程将创建寄存器，非时钟进程将创建锁存器.

A properly implemented clocked process will create registers where an unclocked process would create latches.

并且寄存器不同于锁存器，尤其是我们预测它们时序的能力；以及在 FPGA 中得到更好的支持，所以这通常是一件好事.

And registers are different from latches, especially in our ability to predict their timings; as well as being better supported in FPGAs, so this is usually a Good Thing.

正确实施"意味着只有时钟和(可能)重置)在敏感列表中.

"Properly implemented" means that ONLY Clock and (maybe) Reset) are in the sensitivity list.

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