敏感列表 VHDL 进程 [英] sensitivity list VHDL process

问题描述

我正在尝试使用 Peter Ashenden 的《VHDL 设计师指南》一书来学习 VHDL，但似乎无法摆脱我错过了与敏感度列表相关的基本项目的感觉.

I'm trying to learn VHDL using Peter Ashenden's book 'The Designer's Guide to VHDL', but can't seem to shake the feeling that I have missed a fundamental item related to sensitivity lists.

例如，问题是编写一个模型，该模型表示具有整数输入和输出的简单 ALU，以及类型为 bit 的函数选择输入.如果函数选择为 '0'，则 ALU 输出应为输入，否则输出应该是输入的差值."

for example a question is "Write a model that represents a simple ALU with integer inputs and output, and a function select input of type bit. if the function select is '0', the ALU output should be the sum of the inputs otherwise the output should be the difference of the inputs."

我的解决方案是

entity ALU is

  port (
    a : in  integer;                    -- A port
    b : in  integer;                    -- B port
    sel : in bit;                       -- Fun select
    z  : out integer);                  -- result
end entity ALU;

architecture behav of ALU is

begin  -- architecture behav
  alu_proc: process is
  variable result : integer := 0;
  begin  -- process alu_proc
    wait on sel;
    if sel = '0' then
      result := a + b;
    else
      result := a - b;
    end if;
    z <= result;
  end process alu_proc;
end architecture behav;

与测试台

entity alu_test is
end entity alu_test;

architecture alu_tb of alu_test is
signal a, b, z : integer;
signal sel : bit;
begin  -- architecture alu_tb

  dut: entity work.alu(behav)
    port map (a, b, sel, z);

  test_proc: process is
  begin  -- process test_proc

  a <= 5; b <= 5; wait for 5 ns; sel <= '1'; wait for 5 ns;
  assert z = 0;

  a <= 10; b <= 5; wait for 5 ns; sel <= '0'; wait for 5 ns;
  assert z = 15;

  wait;
  end process test_proc;
end architecture alu_tb;

我的问题与流程中的敏感度列表有关.由于它对选择位的变化很敏感，我必须按顺序执行这些功能，首先是减法，然后是加法，然后在测试台上再次减法.在这个问题中，我觉得你应该能够按顺序进行几次加法，之间没有减法.当然，我可以添加一个使能信号并使进程对此敏感，但我认为应该在问题中说明这一点.我是否遗漏了语言中的某些内容，或者我的解决方案正确"了吗?

my issue has to do with the sensitivity list in the process. Since it is sensitive to changes of the select bit I must do the functions sequentially, first an subtraction, then an addition then a subtraction again in the test bench. In the question I get the feeling that you should be able to do several additions sequentially, no subtraction between. Of course I can add an enable signal and have the process be sensitive to that but I think that should be told in the questions then. Am I missing something in the language or is my solution "correct"?

推荐答案

ALU 过程的问题是 wait on sel; 不包括a 和 b，这样进程就不会被唤醒，输出也不会在这些输入的变化时重新计算.解决此问题的一种方法是添加 a 和'b' 到 wait 语句，例如:

The problem with the ALU process is that the wait on sel; does not include a and b, thus the process does not wake up and the output is not recalculated at changes to these inputs. One way to fix this is to add a and ´b´ to the wait statement, like:

wait on sel, a, b;

然而，为进程写这个的常用方法是使用敏感列表，这是 process 关键字之后的信号列表，因此不包含wait 语句.

However, the common way to write this for processes is with a sensitivity list, which is a list of signals after the process keyword, thus not with the wait statement.

Ashendens book 3rd edition 第 68 页描述了一个敏感列表:

Ashendens book 3rd edition page 68 describes that a sensitivity list:

process 语句在关键字 process 之后包含一个敏感列表.这是进程敏感的信号列表.当任何一个这些信号改变值，进程恢复并执行顺序声明.执行完最后一条语句后，进程挂起再次.

The process statement includes a sensitivity list after the keyword process. This is a list of signals to which the process is sensitive. When any of these signals changes value, the process resumes and executes the sequential statements. After it has executed the last statement, the process suspends again.

敏感列表的使用等同于 wait 语句也被描述在第 152 页的 Ashendens 书中.

The use of sensitivity list as equivalent to wait statement is also described in Ashendens book on page 152.

如果进程被重写为使用敏感列表，它将是:

If the process is rewritten to use a sensitivity list, it will be:

alu_proc: process (sel, a, b) is
begin  -- process alu_proc
  if sel = '0' then
    z <= a + b;
  else
    z <= a - b;
  end if;
end process alu_proc;

请注意，我删除了 result 变量，因为 z 输出可以作为在这种情况下可以直接分配.

Note that I removed the result variable, since the z output can just as well be assigned directly in this case.

当计算中使用的任何值时，上面将重新计算 z更改，因为计算 z 的所有参数都包含在敏感列表.以这种方式进行这种连续计算的风险，是如果在敏感列表中忘记了一个或多个参数，如果忘记的参数发生变化，则不会重新计算 z 的新值.

The above will recalculate z when any of the values used in the calculation changes, since all the arguments for calculating z are included in the sensitivity list. The risk of doing such continuous calculations in this way, is that if one or more of the arguments are forgotten in the sensitivity list, a new value for z is not recalculated if the forgotten argument changes.

VHDL-2008 允许自动包含所有信号和端口如果使用 all ，则敏感度列表如下:

VHDL-2008 allows automatic inclusion of all signals and ports in the sensitivity list if all is used like:

alu_proc: process (all) is

最后的评论，然后是一个简单的异步计算过程，比如对于所示的 ALU，如果生成z 是这样写的:

A final comment, then for a simple process doing asynchronous calculation, like for the shown ALU, it is possible to do without a process, if the generation of z is written like:

z <= (a + b) when (sel = '0') else (a - b);

使用并发分配，像上面一样，可以跳过敏感性列表，从而有可能忘记其中一个信号或端口这是计算的一部分.

Using a concurrent assignment, like the above, make it possible to skip the sensitivity list, and thus the risk of forgetting one of the signals or ports that are part of the calculation.

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