VHDL 中的最小敏感度列表 [英] Minimal sensitivity list in VHDL

问题描述

我有这个 VHDL 代码:

I have this VHDL code:

  entity Element is port(
   clk, D, E, F, G: in std_logic;
   Qout: out std_logic);
   end Element;

   architecture beh of Element is
   signal Qint: std_logic;
   begin

    process(...)
       variable sel: std_logic_vector(1 downto 0);
    begin
       if D='1' then
          Qint<= '0';
       elsif E='1' then
          Qint<= '1';
       elsif rising_edge(clk) then
          sel:=F&G;
          case sel is
            when "00"=> Qint<= not Qint;
            when "01"=> Qint<= not Qint;
            when "10"=> Qint<= '0';
            when "11"=> Qint<= Qint;
            when others=> null;
          end case;
       end if;
    end process;

   Qout<= Qint;

   end beh;

我的问题是:如果我想要最小敏感度列表，我必须在敏感度列表中写入哪些信号?

My question is: Which of this signals I must write in sensitivity list if I want MINIMAL sensitivity list?

推荐答案

您必须在敏感度列表中包含所有读取的信号，而不是在您的进程的时钟部分内.

You have to include in your sensitivity list all signals that are read and not inside a clocked part of your process.

您异步读取 D 和 E.您将 clk 作为寄存器的一部分读取.因此，您必须包含它们.

You read D and E asynchronously. You read clk as part of your register. Therefore you have to include them.

process (D, E, clk)
begin
end process;

注意:在VHDL-2008中，最小敏感度列表是

Notice: In VHDL-2008, the minimal sensitivity list is

process (all)
begin
end process;

关于敏感度列表的更多信息.

A bit more about the sensitivity list in general.

VHDL 中的仿真是在确定性周期中完成的.对于每个信号分配，所有相关信号也必须更新，因为这是硬件发生的事情.

Simulation in VHDL is done in deterministic cycles. For every signal assignment all dependent signals will have to be updated as well, because that's what happens in hardware.

模拟器(例如modelsim、isim)将逐步执行您的HDL，确定所有信号变化，然后确定哪些其他信号依赖于这些变化.然后模拟第二组变化并找到另一组相关信号，依此类推.模拟一直持续到 a) 达到稳定状态或 b) 已通过最大迭代次数.

The simulator (e.g. modelsim, isim) will step through your HDL, determine all signal changes, then determine what other signals depend on these changes. The second set of changes is then simulated and another set of dependent signals is found and so on. The simulation goes on until a) a steady state is reached or b) a maximum number of iterations has passed.

现在，有了大型设计并且需要重新评估每个信号分配的每个过程，复杂性爆炸.为了防止这种情况，每个进程只在其敏感度列表中的信号更改时才重新评估.过去，软件无法自动检测给定进程需要侦听(或可以忽略)的所有信号，因此用户必须通过敏感度列表给工具一个提示.

Now, with a large design and the need to re-evaluate every process on every signal assignment, the complexity explodes. To prevent that, every process is only re-evaluated when a signal in its sensitivity list changes. Back in the day, software could not automatically detect all the signals it needed to listen to (or could ignore) for a given process, so the user had to give the tools a hint via the sensitivity list.

如今，有了 VHDL-2008，软件变得如此智能，CPU 变得如此快速，以至于仿真软件可以简单地分析所有 HDL 并自行确定相关性.

Nowadays, with VHDL-2008, software got so smart and CPUs got so fast, that simulation software can simply analyze all of the HDL and determine dependencies by itself.

现在，为什么Qint没有在敏感列表中?因为 Qint 中的变化直到 clk 的下一个上升沿才会传播到其他信号.它只在 clk 的边缘精确采样.

Now, why is Qint not in the sensitivity list? Because changes in Qintdon't propagate to other signals until the next rising edge of clk. It is only sampled exactly at the edge of clk.

因此，Qint 仅用于进程的时钟部分，它本身确实确定另一个信号的状态.

Therefore, Qint is only used in the clocked part of the process and by itself does determine the state of another signal.

这就是您对寄存器的期望.在时钟上升/下降时对输入进行采样，然后存储并传播到输出.在时钟边沿之间，输入信号可以(并且经常会)改变，但很快就会稳定到有效的逻辑状态.

And that's what you expect for a register. The input is sampled when the clock rises/falls and then stored and propagated to the output. In-between clock edges, the input signal can (and often will) change, but quickly settle to a valid logic state.

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