verilog 总是空的敏感列表 [英] verilog always empty sensitivity list

问题描述

always clk <= #5 !clk;

这似乎不起作用，并且 VCS 会出现内存不足"错误

Seems this doesn`t work and get a "out-of-memory" errors with VCS

这背后的原因是什么?我感觉 VCS 无法摆脱它为 clk 安排的事件.但不知道为什么?

What's the reason behind this? I have the feeling the VCS can't get out of the event it scheduled for clk. but don't know why?

推荐答案

您收到内存不足"错误，因为这是一个向调度程序添加未来事件的非阻塞无限循环.

You are getting an "out-of-memory" error because it is an non-blocking infinite loop adding future events to the scheduler.

always 在功能上等同于 initial while(1)(无限循环).<= #5 不消耗时间，它会在未来安排更新.循环中没有时间阻塞延迟.

always is functionally equivalent to initial while(1) (an infinite loop). <= #5 doesn't consume time, it schedules an update in the future. There is no time blocking delays in the loop.

在没有时间阻塞延迟的情况下，模拟器会在相同的时间步中继续执行相同的循环.在当前时间步中的所有操作完成或暂停之前，模拟不会移动到下一个时间步.最终模拟器将耗尽内存并出错.如果检测到无限循环，某些模拟器可能会提前退出.

Without a time blocking delay the simulator keeps executing the same loop in the same time step. The simulate will not move to the next time step until all operations in the current time step are complete or suspended. Eventually the simulator will run out of memory and error out. Some simulators may exit out early if an infinite loop is detected.

通常，时钟是通过 LHS 延迟和阻塞语句生成的.示例:

Typically, clocks are generated with LHS delays and with blocking statements. Examples:

reg clk = 1'b1; // or 1'b0
always #5 clk = !clk;

或

reg clk;
initial begin
  clk = 1'b1; // or 1'b0
  forever #5 clk = !clk;
end

这篇关于verilog 总是空的敏感列表的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！