在 verilog 中总是阻塞有问题 [英] having trouble with always block in verilog

问题描述

我目前正在制作一款可以设置开始时间的手表，但遇到 always@() 问题

I'm currently making a watch that we can set times to start and having a problem with always@()

always @ (posedge clk or posedge reset or posedge sw3 or posedge sw4) begin
    if(reset == 1) begin //reset signal is not a pulse therefore this could do the thing needed for keep pressing the reset button
        tmp_second = 0;
        tmp_minute = 0;
        tmp_hour = 0;
    end

以上只是完整代码的一部分，其余部分是关于通过 sw3 和 sw4 设置时间但是当我尝试合成此模块时出现以下错误

the above is just a part of the full code and the rest of it is about setting the time by sw3 and sw4 but when I try to Synthesize this module the following Error comes up

ERROR:Xst:2089 - "first_mode.v" line 69: This sensitivity list construct will match none of the supported FF or Latch templates.

如果我改变了always块

if I change the always block like

always @ (posedge clk or posedge reset) begin

我没有收到错误消息，但我希望posedge sw3 和sw4 独立于clk 工作

I dont get the error message but I want posedge sw3 and sw4 to work independently from clk

有没有办法使用always块，包括那些4

would there be any way to use always block including those 4

推荐答案

在综合时，通过坚持模板来保持一致是明智的.这是一个具有异步复位的时序逻辑模板，所有综合工具都应该理解:

When synthesising, it is wise to be consistent by sticking to a template. Here is one such template for sequential logic with an asynchronous reset, which all synthesis tools should understand:

always @(posedge CLOCK  or posedge RESET)  // or negedge
  begin
    // PUT NO CODE HERE
    if (RESET == 1'b1)  // or (RESET == 1'b0) for an active-low reset
      // set the variables driven by this always block to their reset values
      // MAKE SURE YOU USE NON-BLOCKING ASSIGNMENTS ( <= )
    else
      // do things that occur on the rising (or falling) edge of CLOCK
      // stuff here gets synthesised to combinational logic on the D input
      // of the resulting flip-flops
      // MAKE SURE YOU USE NON-BLOCKING ASSIGNMENTS ( <= )
end

以下是没有异步复位的顺序过程的相应模板:

Here is the corresponding template for a sequential process without an asynchronous reset:

always @(posedge CLOCK)  // or negedge
  begin
    // do things that occur on the rising (or falling) edge of CLOCK
    // stuff here gets synthesised to combinational logic on the D input
    // of the resulting flip-flops
    // MAKE SURE YOU USE NON-BLOCKING ASSIGNMENTS ( <= )
end

最后，这是组合逻辑的模板:

And finally, here is the template for combinational logic:

always @(*)
  begin
    // implement your combinational logic here
    // MAKE SURE YOU USE BLOCKING ASSIGNMENTS ( = )
end

您的代码不符合这三个模板中的任何一个模板，也不符合任何其他模板.这就是为什么你的综合工具不理解它.

Your code does not comform to any of these three templates nor any other. That is why you synthesis tool doesn't understand it.

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