Verilog 总是阻塞，没有敏感列表 [英] Verilog always block with no sensitivity list

问题描述

没有敏感性列表的 always 块是否会推断组合逻辑，就像 always_comb 或 always @(*) 一样?例如代码:

would an always block with no sensitivity list infer a combinational logic, just the same as always_comb or always @(*)? Eg code:

always begin
if (sig_a)begin
 @(posedge sig_b); // wait for a sig_b posedge event
 @(negedge sig_b); // then wait for a sig_b negedge event
 event_true=1;  
end

if (event_true)begin
  @((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true
  yes =1;
 end
 else yes =0;

end

推荐答案

综合工具需要特定的模板编码风格来综合您的代码.大多数只允许在 always 块的开头使用单个显式事件控件.一些允许多个事件控制的高级综合工具只允许同一时钟边沿出现多次.

Synthesis tools require a specific template coding style to synthesize your code. Most only allow a single explicit event control ar the beginning of an always block. Some of the higher-level synthesis tools that do allow multiple event controls only allow multiple occurrences of the same clock edge.

模拟工具没有这些限制，并且会尝试执行您可以编译的任何合法语法.顺便说一句，您的 @((sig_c==1)&&(sig_a==0)) 意味着等待表达式更改值，而不是等待它变为真.wait(expr) 结构意味着等待表达式变为真.

Simulation tools don't have these restrictions and will try to execute whatever legal syntax you can compile. BTW, your @((sig_c==1)&&(sig_a==0)) means wait for the expression to change value, not wait for it to become true. The wait(expr)construct means wait for the expression to become true.

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