VHDL 过程风格 [英] VHDL process style

问题描述

我一直在阅读这里的各种问题，因为我正在学习 VHDL 并且一直在寻求改进.然而，这条评论让我很好奇:

I have been reading through various questions on here, as I am learning VHDL and always looking to improve. However, this comment made me curious:

简单状态机问题

在我在大学的简短 VHDL 课程中，有人告诉我，分离进程是最好的形式，以分离同步方面.

I was told, in my brief VHDL course at university, that separate processes was best form, to separate the synchronous aspects.

显然这是个人喜好，但我希望一些更有经验的用户能够根据自己的喜好阐明优缺点?一种比另一种更常见吗?

Obviously this is personal preference, but I was hoping that some more experienced users may be able to shed some light on the pros/cons, with their own preferences? Is one more common than the other?

谢谢！

推荐答案

嗯，因为是我说的你所链接的内容......我最好发表评论 :)

Well, as it was me that said what you've linked to... I'd better comment :)

坏事(恕我直言)，如果你把东西放在不同的进程中:

Bad things (IMHO) if you put things in separate processes:

• 你必须认真地更新你的敏感列表
• 你必须为每个输出提供默认值，除非你想要异步锁存器(你通常不需要)
• 逻辑是分开的，所以如果你给状态机添加一个状态，你必须把新状态放在两个进程中
• 如果您希望一个信号既可以注册也可以未注册使用，那么您最终会复制它.只需一个流程，您就可以使用变量来实现这一点.
• 有些人认为它更难阅读.

• you have to keep your sensitivity list religiously up to date
• You have to provide defaults for every output, unless you want asynchronous latches (which you usually don't)
• The logic is split up, so if you add a state to a state machine, you have to put the new state in both processes
• If you want a signal to be used both registered and unregistered, you end up duplicated it. With a single process you can use variables to achieve this.
• some people think it's harder to read.

好东西:

• 您可以取消注册状态的输出".这对于减少延迟很有好处，但对于几乎所有目的，您希望在每个块的输出上进行注册，以便更轻松地安排会议时间.
• 有些人认为它更容易阅读

• You can have the "output" of a state unregistered. This can be good for reducing latency, but for almost all purposes you want registers on the output of each block to make meeting timing easier.
• Some people think it's easier to read

我的观点是，像您听到的那样的法令(保持分离")源于合成器不太擅长区分逻辑与触发器的时代，因此将触发器放在时钟过程中是有意义的.

My opinion is that edicts like you heard ("keep it separate") stem from the days when synthesisers weren't very good at differentiating the logic from the flops, so putting just the flops in clocked processes made sense.

此外，这种方法与那个时代的人们在拥有 HDL 之前绘制原理图的方式相匹配.

Furthermore, that approach matched the way people of that era drew schematic diagrams before they had HDLs.

如今，合成器可以处理时钟过程中任意复杂的逻辑.而且我可以按照有意义的方式编写它，而不必明确说明每一点逻辑所在的位置.只有当时机真的很紧时，我才必须认真考虑将翻牌和逻辑放在正确的位置.

These days, synthesisers can deal with arbitrarily complex logic in clocked processes. And I can write it the way that makes sense without having to be explicit about where each tiny bit of logic sits. Only when timing is really tight do I have to think really hard about placing flops and logic in just the right places.

我的规则"是:

• 保持可读性
• 如果它满足要求(例如电源、时序和功能正常)，那么您就完成了.
• 如果没有，那么然后玩不可读的技巧

• Keep it readable
• If it meets the requirements (eg power, timing and functions OK), you're done.
• If not, then and only then play unreadable tricks

很喜欢写软件:)

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