vhdl 乘数 [英] vhdl multipliers

问题描述

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

architecture Behavioral of Lab3_Adder1 is

    SIGNAL c : STD_LOGIC_VECTOR (4 DOWNTO 0);

begin
    c(0) <= cin;
    s <= a XOR b XOR c (3 DOWNTO 0);
    c (4 DOWNTO 1) <= (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
    cout <= c(4);
end Behavioral;

您好，这是我第一次使用这个论坛.我正在 VHDL 上做华莱士树乘法.上面的代码是一个全加器的代码.我想知道我们如何在主代码中调用函数/组件?(就像在 C 编程中一样).我会在我的主代码中调用这个全加器.(如果有任何错误，对不起我的英语，我是法语)

Hello, it's the first time im using this forum. I'm doing a wallace tree multiplication on VHDL. The code above is the code for a full adder. I would like to know how do we call a function/component in a main code ? (like in C programing). I would to call this full adder in my main code. (Sorry for my english if there is any mistake, im french)

推荐答案

您可以像在 C 中一样在 VHDL 中调用函数 - 初始化常量、信号或变量，或者作为进程中的顺序语句.但这并不重要.

You call functions in VHDL just as you do in C - either to initialise constants, signals or variables, or as sequential statements within a process. But that's not important just now.

但是你不调用组件！这就像在 C++ 中调用一个对象——这完全没有意义！

But you don't call components! That would be like calling an object in C++ - it makes absolutely no sense!

在 VHDL 中，您可以实例化组件或(更简单！)实体，并使用信号来互连它们的端口.这(非常非常粗略地)更像是在面向对象的语言中声明对象和发送消息.这称为结构 VHDL"，通常出现在 VHDL 设计的顶层，用于创建和互连 CPU、内存接口、FFT 处理器等组件.

In VHDL you can instantiate components or (simpler!) just entities, and use signals to interconnect their ports. This is (very very crudely) more like declaring objects and sending messages in an object oriented language. This is called "structural VHDL" and often appears at the top level of a VHDL design, to create and interconnect components like CPU, memory interface, FFT processor etc.

给定你的实体

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

我可以构建一个 8 位加法器，例如:

I could build an 8-bit adder for example as follows:

entity Adder_8bit is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           s : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out  STD_LOGIC);
end Adder_8bit;

architecture Structural of Adder_8bit is

signal carry_int : std_logic;   -- between lower and upper halves

begin
-- We need to create and connect up two adders

LSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => cin,
           a  => a(3 downto 0),
           b  => b(3 downto 0),
           s  => s(3 downto 0),
           cout => carry_int
    );
MSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => carry_int,
           a  => a(7 downto 4),
           b  => b(7 downto 4),
           s  => s(7 downto 4),
           cout => cout
    );

end Structural;

这篇关于vhdl 乘数的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！