1，2或3过程对于VHDL中的FSM意味着什么？ [英] What does 1-, 2-, or 3-process mean for an FSM in VHDL?
问题描述
似乎有一些关于如何在VHDL中对有限状态机（FSM）进行编码的争论。人们谈论1进程，2进程或3进程FSM，好像每个人都知道它的意思和每个进程做什么。然而，我一直无法找到一个精确的定义，存在的例子似乎是矛盾的。
It seems like there is quite some debate about how to code finite state machines (FSMs) in VHDL. People talk about 1-process, 2-process, or 3-process FSMs as if everyone knew exactly what it means and what each process does. However, I've been unable to find a precise definition, and the examples that exist seem to be contradictory.
这是一个客观的问题：每个FSM风格（1过程，2过程，3过程）的代码有什么区别？我明白，有一个个人偏好的组成部分，但当然可以客观地回答问题，并列出每种方法的优点。
This is an objective question: What is the difference in terms of code for each FSM style (1-process, 2-process, 3-process)? I understand that there is a component of personal preference, but certainly it is possible to answer the question objectively and list the advantages of each approach.
谢谢，
推荐答案
我试着回答，如果它很难，因为每个人都编码他喜欢和硬件的工作条件的功能，外部路径，...）。
I try to answer also if it's hard because every person code how he likes and in function of the condition where the hardware has to work (frequency, external paths, ...).
在状态机中有一些元素：
In a state machine you have some elements:
- 输入
- 输出
- 当前状态
- li>
- the inputs
- the outputs
- the current state
- the next state
下一状态取决于当前状态和输入。为了不具有组合循环，需要对时钟信号的事件采样下一个状态，以使其变为当前状态。所以，你需要一个VHDL过程来创建状态的触发器。在这个过程中，你可以把你需要的所有逻辑计算下一个状态。如果你的输出只取决于你不需要别人处理的状态。
Next state depends from current state and inputs. To don't have combinatory loops, you need to sample the next state on the event of a clock signal so that it becomes the current state. So, you need a VHDL process to create the flip-flop for the state. In this process you can put all logic that you need to calculate the next state. If your outputs depends only from state you don't need others process.
当逻辑不是很容易的时候，我不喜欢把相同的过程组合逻辑（我喜欢这样，但它不是强制的）所以，通常我拆分FSM在两个过程：第一个非常简单的过程，采样下一个状态具有当前的一个组合过程，其中我计算所有输出和下一个状态作为输入和当前状态的函数。
I don't like to put in the same process combinatory logic when the logic is not very easy (I like so, but it's not mandatory!) so, normally I split the FSM in two process: a first very easy process that sample the next state to have the current one, and one combinatory process where I calculate all outputs and the next state as function of inputs and current state.
在相同的情况下，输出需要采样：例如，当频率问题时，路径从外部，或当输出具有大负载时。在这种情况下，您可以在第一个进程中添加所有必需的触发器，您可以在其中采样下一个状态或创建一个或多个专用进程。
In same cases, the outputs need to be sampled: for example, when for problem of frequency, you need to separate the internal paths from external ones, or when the outputs have a big load. In this case, you can add all necessary flip-flops in the first process where you sample the next state or create one or more dedicated process.
但是您也可以许多变体作为过程的数量：我在一个代码中工作，其中每个信号在专用过程中计算，所以生成的状态机有20/30过程。
But you can have also many variants as number of process: I worked in a code, where every signal is calculated in a dedicated process so the resulting state machine had 20 / 30 process.
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