VHDL 中的进程是可重入的吗? [英] Is process in VHDL reentrant?

问题描述

VHDL 中的进程是否可能有两个或多个顺序运行?

Is it possible two or more sequential run for a process in VHDL?

如果另一个事件发生(在敏感信号列表上)而进程的顺序执行尚未完成，会发生什么?

What will happen if another event happen (on sensitivity signal list) while the sequential execution of a process is not completed ?

是否有可能或者我的VHDL模型是完全错误的?

Is it possible or my VHDL model in mind for process is completely wrong?

推荐答案

进程运行时不会发生任何事件！

No event will ever occur while a process is running!

当一个进程被一个事件唤醒时，它运行到完成(结束进程")或一个明确的等待"语句，然后进入睡眠状态.从理论上讲，这需要零时间.这意味着如果您的流程中有循环，它们将被有效地完全展开，并且当您综合时，您将生成足够的硬件来并行运行每个迭代.此外，任何过程、函数等都占用零时间 - 除非它们包含显式的等待"语句(在这种情况下，进程在等待"处挂起，就像过程已被内联一样).

When a process is woken by an event, it runs to completion ("end process") or an explicit "wait" statement, and goes to sleep. This takes, notionally, ZERO time. Which means that if you have loops in your process, they are effectively unrolled completely, and when you synthesise, you will generate enough hardware to run EVERY iteration in parallel. Also, any procedures, functions etc, take zero time - unless they contained an explicit "wait" statement (in which case the process suspends at the "wait", as if the procedure had been inlined).

在整个过程中，所有信号都具有它们在进程唤醒时最初拥有的值，并且任何信号分配都被存储起来，以备后用.(变量立即更新；过程中的后续语句会看到新值).

Throughout this process, all signals have the value they originally had when the process woke up, and any signal assignments are stored up, to happen later. (Variables update immediately; later statements in the process see the new value).

当进程挂起时(在等待"或结束进程")，在所有其他进程也挂起之前什么都不会发生.(但请记住，它们都需要零时间！).如果一个进程在结束进程"时挂起，当它的敏感列表唤醒它时，它将从头重新启动.如果它在明确的等待"时挂起，那么等待"将指定一个事件或未来时间，这将在等待"之后重新启动.(注意:1:不要在同一过程中混合敏感列表和等待样式！2:等待直到某些事件可合成(尽管某些工具可能会反对)；等待一段时间只是模拟)

When the process suspends (at "wait" or "end process"), nothing happens until ALL the other processes also suspend. (But remember they all take zero time!). If a process suspends at "end process" it will restart from the beginning when its sensitivity list wakes it up. If it suspends at an explicit "wait", that "wait" will specify an event or future time, which will restart it after the "Wait". (NOTES: 1 : do not mix the sensitivity list and Wait styles in the same process! 2: Wait Until some event is synthesisable (though some tools may object) ; Wait for some time is simulation only)

然后执行所有信号分配.由于所有进程都处于休眠状态，这消除了所有竞争条件和计时风险.其中一些分配(如时钟的1")会导致将事件安排在对它们敏感的进程上.

THEN all the signal assignments are performed. Since all processes are asleep, this eliminates all race conditions and timing hazards. Some of these assignments (like '1' to a clock) will cause events to be scheduled on processes sensitive to them.

在所有信号分配完成后，时间向前一个无限短的滴答声(称为增量周期)，然后所有有预定事件的进程都被唤醒.

After all the signal assignments are done, the time steps forward one infinitely short tick (called a delta cycle), and then all the processes with scheduled events are woken.

这种情况一直持续到一个 delta 循环发生，在该循环中没有安排新的事件，最后模拟可以按实时步长进行.

This continues until a delta cycle occurs in which NO new events are scheduled, and finally the simulation can advance by a real time step.

因此

process(clk)
begin
if rising_edge(clk) then
   A <= B;
   B <= A;
end if;
end process;

在 VHDL 中是无危害的.

is hazard-free in VHDL.

如果您需要使用 Verilog，请注意其中一些情况会有所不同，并且您不能依赖模拟结果中相同级别的可预测性.

If you ever need to use Verilog, be aware that some of this happens differently there, and you cannot rely on the same level of predictability in simulation results.

当然，在综合中，我们会生成硬件，这需要一些实时时间来执行此过程.然而，综合和后端工具(布局和布线)保证要么忠实地遵守这个模型，要么失败并报告失败的原因.例如，他们会将所有实际延迟相加并验证总和是否小于您指定的时钟周期.(除非您将时钟速度设置得太高！).

In synthesis, of course, we generate hardware which will take some real time to execute this process. However, the synthesis and back-end tools (place and route) guarantee to either obey this model faithfully, or fail and report why they failed. For example, they will add up all the real delays and verify that the sum is less than your specified clock period. (Unless you have set the clock speed too high!).

所以结果是，只要工具报告成功(并且您正确设置了时钟速度等时序约束)，您就可以假装上述零时间"模型为真，并且真实的硬件行为将与模拟匹配.保证，除非工具错误！

So the upshot is, as long as the tools report success (and you are setting the timing constraints like clock speed correctly) you can pretend the above "zero time" model is true, and the real hardware behaviour will match the simulation. Guaranteed, barring tool bugs!

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