VHDL 中的动态信号创建和 VHDL 错误的解决方案:“进程"附近的语法错误 [英] Dynamic signal creation in VHDL and solution of VHDL error: Syntax error near "process"

问题描述

我是 VHDL 世界的新手，我收到这个错误消息，说接近进程的语法错误.我检查了解决方案，发现可能缺少 end if 语句，但在我的代码中我没有这个问题.

I'm new to the world of VHDL and I'm getting this error saying Syntax error near process. I checked for the solutions and found that there may be a missing end if statement but in my code I'm not having that problem.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
use STD.textio.all;

entity Main_Architecture is
port(
    SEN: out std_logic;
    reset: in std_logic;
    clk: in std_logic
    );
end Main_Architecture;

architecture Behavioral of Main_Architecture is
signal main_counter : std_logic_vector(7 downto 0)  := "00000000";
signal mux: std_logic_vector(1 downto 0) := "00";
signal output  : std_logic_vector(7 downto 0);
signal main_counter_int : integer range 0 to 127:=0;
signal main_generator : std_logic_vector(7 downto 0);


begin
process(main_counter,reset,clk)
    variable x: std_logic;
    variable y: std_logic;
    variable z: integer;
begin
    if(reset = '1') then
        main_counter <= (others => '0');
    end if;

    if(clk'event and clk='1') then

        if(mux="00") then                               --load main counter
            y:= main_counter(0);
            x:= (main_counter(0)XOR main_counter(6) XOR main_counter(7));
            main_counter(7 downto 1) <= main_counter(6 downto 0);
            main_counter(0)<=x;
            main_counter <= main_counter+'1';
            output(0)<=y;
            output(1)<=main_counter(0);
            output(2)<=main_counter(1);
            output(3)<=main_counter(2);
            output(4)<=main_counter(3);
            output(5)<=main_counter(4);
            output(6)<=main_counter(5);
            main_counter_int<=conv_integer(output);
            if(main_counter >= "11111111") then
                mux <= "01";
            end if;
        end if;

        if(mux="01") then
            if(main_counter_int < 2) then
                z:=1;
            else if(main_counter_int < 4) then
                z:=2;
            else if(main_counter_int < 8) then
                z:=3;
            else if(main_counter_int < 16) then
                z:=4;
            else if(main_counter_int < 32) then
                z:=5;
            else if(main_counter_int < 64) then
                z:=6;
            else if(main_counter_int < 128) then
                z:=7;
            end if;


        end if;

    end if;

end process;    -------- LINE 104  -------

end Behavioral;

我还想创建一个大小从 z 到 0 的 std_logic_vector.即大小为 z+1 的向量.我该怎么做?

Also I want to create a std_logic_vector which has a size from value z to 0. i.e. A vector of size z+1. How can i make it?

推荐答案

问题第 1 部分

在不查看代码中的任何其他问题的情况下，我认为问题出在这一部分，我已经对其进行了重新格式化以显示您遗漏了多少个end if"语句:

Question part 1

Without looking into any other issues in your code, I think the problem is this section, which I have re-formatted to show how many 'end if' statements you are missing:

    if(mux="01") then
        if(main_counter_int < 2) then
            z:=1;
        else
            if(main_counter_int < 4) then
                z:=2;
            else
                if(main_counter_int < 8) then
                    z:=3;
                else
                    if(main_counter_int < 16) then
                        z:=4;
                    else
                        if(main_counter_int < 32) then
                            z:=5;
                        else
                            if(main_counter_int < 64) then
                                z:=6;
                            else
                                if(main_counter_int < 128) then
                                    z:=7;
                                end if;


    end if;

我想你可能想使用 elsif 而不是 else if.

I think you probably wanted to use elsif instead of else if.

对于您问题的第二部分，假设您想生成可以在硬件中实现的代码，则没有运行时大小的 std_logic_vector 这样的东西.您能做的最好的事情是使您的向量具有它可能需要的最大大小，然后仅根据z"的值分配或使用其中的一部分.

For the second part of your question, assuming you want to produce code that can be realised in hardware, there is no such thing as a run-time sized std_logic_vector. The best you can do is to make your vector have the maximum size that it could need, then only assign or use parts of it, based on the value of 'z'.

USE ieee.std_logic_arith.ALL;

这不是一个真正的"标准库，还有很多其他的答案人们建议不要使用这个库.如果您需要执行数学函数(例如 +)，USE ieee.numeric_std.all;，然后创建有符号或无符号类型的信号.在您的示例中，main_counter 将被声明为 signal main_counter : unsigned(7 downto 0) :="00000000";.然后可以对这个信号执行 + 之类的操作，对于是否应该签名没有歧义.

This is not a 'true' standard library, and there are many other answers where people recommend against using this library. If you need to perform math functions (e.g. +), USE ieee.numeric_std.all;, then create signals of type signed or unsigned. In your example, main_counter would be declared signal main_counter : unsigned(7 downto 0) := "00000000";. Operations like + can then be performed on this signal, with no ambiguity as to whether it is supposed to be signed or not.

最后，部分:

        output(0)<=y;
        output(1)<=main_counter(0);
        output(2)<=main_counter(1);
        output(3)<=main_counter(2);
        output(4)<=main_counter(3);
        output(5)<=main_counter(4);
        output(6)<=main_counter(5);

可以使用连接运算符 & 更紧凑地编写为

could more compactly be written using the concatenation operator & as

        output(6 downto 0) <= main_counter(5 downto 0) & y;

旁注:output(7) 似乎从未被分配过.

Side note: output(7) doesn't seem to ever be assigned.

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