VHDL 语法错误与 if then process [英] VHDL Syntax error with if then process
问题描述
library ieee;使用 ieee.std_logic_1164.all;实体 basic_shift_register_with_multiple_taps 是通用的(数据宽度:自然:= 8);港口(clk : 在 std_logic 中;启用:在 std_logic 中;sr_one : 在 std_logic_vector((DATA_WIDTH-1) downto 0);sr_two : 在 std_logic_vector((DATA_WIDTH-1) downto 0);sr_out : 输出 std_logic_vector(2*(DATA_WIDTH-1) 到 0));最终实体;basic_shift_register_with_multiple_taps 的架构 rtl 是信号 sig_out :std_logic_vector(2*(DATA_WIDTH-1) downto 0);变量计数:整数:= 0;变量 count1 : 整数 := 0;开始进程(时钟,启用,sr_one,sr_two,sig_out)开始if(enable = '0' or count = 16) then计数:= 0;计数1:= 0;else if (clk'event and clk='1') thensig_out(count) <= sr_one(count1);计数 := 计数 + 1;else --if (clk'event and clk='0') then--sig_out(count) <= sr_two(count1);计数 := 计数 + 1;万一;计数 1 := 计数 1 + 1;(54) 结束进程;sr_out <= sig_out;(58) 结束 rtl;
错误:
<块引用>错误 (10500):teste.vhd(54) 文本process"附近的 VHDL 语法错误;期待如果"
错误 (10500):teste.vhd(58) 文本rtl"附近的 VHDL 语法错误;期待如果"
你的问题是你的第二个 if 语句
if (clk'event and clk='1') then
没有与之关联的 end if
.因此,当编译器到达第 54 行时,它会在它期望的 end if
之前遇到 end process
.而不是这个
if(enable = '0' or count = 16) then计数:= 0;计数1:= 0;else if (clk'event and clk='1') thensig_out(count) <= sr_one(count1);计数 := 计数 + 1;else --if (clk'event and clk='0') then--sig_out(count) <= sr_two(count1);计数 := 计数 + 1;万一;
这样做:
if(enable = '0' or count = 16) then计数:= 0;计数1:= 0;别的if (clk'event and clk='1') 那么sig_out(count) <= sr_one(count1);计数 := 计数 + 1;else --if (clk'event and clk='0') then--sig_out(count) <= sr_two(count1);计数 := 计数 + 1;万一;万一;
但是,如果您打算对此进行综合,则语法错误是您最不担心的.请参阅此答案.>
library ieee;
use ieee.std_logic_1164.all;
entity basic_shift_register_with_multiple_taps is
generic
(
DATA_WIDTH : natural := 8
);
port
(
clk : in std_logic;
enable : in std_logic;
sr_one : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_two : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_out : out std_logic_vector(2*(DATA_WIDTH-1) downto 0)
);
end entity ;
architecture rtl of basic_shift_register_with_multiple_taps is
signal sig_out :std_logic_vector(2*(DATA_WIDTH-1) downto 0);
variable count : integer := 0;
variable count1 : integer := 0;
begin
process (clk,enable,sr_one,sr_two,sig_out)
begin
if(enable = '0' or count = 16) then
count := 0;
count1 := 0;
else if (clk'event and clk='1') then
sig_out(count) <= sr_one(count1);
count := count + 1;
else --if (clk'event and clk='0') then--
sig_out(count) <= sr_two(count1);
count := count + 1;
end if;
count1 := count1 + 1;
(54) end process;
sr_out <= sig_out;
(58) end rtl;
errors:
Error (10500): VHDL syntax error at teste.vhd(54) near text "process"; expecting "if"
Error (10500): VHDL syntax error at teste.vhd(58) near text "rtl"; expecting "if"
Your problem is that your second if statement
if (clk'event and clk='1') then
has no end if
associated with it. So, when the compiler gets to line 54, it encounters an end process
before the end if
it was expecting. Instead of this
if(enable = '0' or count = 16) then
count := 0;
count1 := 0;
else if (clk'event and clk='1') then
sig_out(count) <= sr_one(count1);
count := count + 1;
else --if (clk'event and clk='0') then--
sig_out(count) <= sr_two(count1);
count := count + 1;
end if;
do this:
if(enable = '0' or count = 16) then
count := 0;
count1 := 0;
else
if (clk'event and clk='1') then
sig_out(count) <= sr_one(count1);
count := count + 1;
else --if (clk'event and clk='0') then--
sig_out(count) <= sr_two(count1);
count := count + 1;
end if;
end if;
However, if you are intending to synthesis this, your syntax error is the least of your worries. See this answer.
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