VHDL值在时钟边沿之外的编码错误 [英] VHDL - coding error of value outside the clock edge

问题描述

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity RAM_controler is 
port(
      clk_50 : in std_logic;
      clk_baud : in std_logic;
      main_reset : in std_logic;
      enable: in std_logic; --active high write enable
      in_data : in std_logic_vector(7 downto 0);
      W_order : out std_logic; 
      R_order : out std_logic;
      Data_OUT : out std_logic_vector(7 downto 0);
      Write_Address_OUT: out std_logic_vector(7 downto 0);  
      Read_Address_OUT: out std_logic_vector(7 downto 0)          
      );
end entity RAM_controler;
architecture Behavioral of RAM_controler is
type state is (reset,operation);
signal state_reg,next_state_reg : state;
signal write_address : std_logic_vector(W-1 downto 0):="00000000"; 
signal next_write_address : std_logic_vector(W-1 downto 0):="00000000";         
begin   
state_change : process(clk_50, main_reset)
begin
    if (main_reset = '1') then
        state_reg <= reset;     
    elsif (rising_edge(clk_50)) then
        state_reg <= operation;
        read_counter <= next_read_counter;
        write_address<= next_write_address;
        read_address <= next_read_address;
    end if;     
end process;

writecounter : process(clk_baud, main_reset,enable) 
begin
    if (main_reset='1') then
        next_write_address <= "00000000";
        Data_OUT <= "ZZZZZZZZ";
        W_order <='0';
        Write_Address_OUT <="ZZZZZZZZ";
    elsif (rising_edge(clk_baud) and enable='1' ) then
        W_order <='1';
        Data_OUT <= in_data;            
        Write_Address_OUT <= write_address;
        if (write_address = "11111111") then
            next_write_address <= "00000000";
        else
            next_write_address <= write_address+1;
        end if;
    else 
        W_order <='0';
        Write_Address_OUT <= "ZZZZZZZZ";
        next_write_address <= write_address+1;
    end if;
end process;        
end Behavioral;

以上代码描述的是RAM控制器。

出题部分为"elsif(RISING_EDGE(CLK_BAUD)AND ENABLE=‘1’)THEN"。

错误：无法将"WRITE_ADDRESS_OUT"寄存器置于RAM_Controller er.vhd中，因为它没有将其值保持在时钟边沿之外

我不知道为什么该点是错误的。

有没有人给我提建议？

谢谢！

推荐答案

如果您在编写顺序逻辑，明智的做法是坚持使用模板。以下是带有异步重置的时序逻辑的一个这样的模板，所有综合工具都应该理解：

process(clock, async_reset)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if async_reset ='1' then  -- or '0' for an active low reset
        -- set/reset the flip-flops here
        -- ie drive the signals to their initial values
    elsif rising_edge(clock) then  -- or falling_edge(clock)
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;        

因此启用不应在敏感度列表中，并且不应在与异步重置相同的IF语句中进行测试，并测试时钟。

您收到此错误的原因：

错误：无法将"WRITE_ADDRESS_OUT"的寄存器设置为 ram_control er.vhd，因为它不会将其值保持在时钟之外 边缘

是因为代码中的最后三个赋值：

            W_order <='0';
            Write_Address_OUT <= "ZZZZZZZZ";
            next_write_address <= write_address+1;

可以发生在时钟的下降沿，或者(因为您还在敏感度列表中启用了)，完全独立于任何时钟。逻辑合成器不能综合那样行为的逻辑。如果您坚持使用模板，就不会遇到这种问题(而且它会让您更仔细地考虑您希望合成器合成什么逻辑)。

因此，我会将您的WritecCounter进程编码如下：

writecounter : process(clk_baud, main_reset) 
begin
    if (main_reset='1') then
        next_write_address <= "00000000";
        Data_OUT <= "ZZZZZZZZ";
        W_order <='0';
        Write_Address_OUT <="ZZZZZZZZ";
    elsif rising_edge(clk_baud) then
        if enable='1' then
            W_order <='1';
            Data_OUT <= in_data;            
            Write_Address_OUT <= write_address;
            if (write_address = "11111111") then
                next_write_address <= "00000000";
            else
                next_write_address <= write_address+1;
            end if;
        else 
            W_order <='0';
            Write_Address_OUT <= "ZZZZZZZZ";
            next_write_address <= write_address+1;
        end if;
    end if;
end process;        

但是，我应该强调，我的代码的行为与您的并不完全相同。我不知道你的设计意图，所以我只能猜测你的意图。如果您打算执行其他行为，那么您将不得不实现它。不管您的设计意图如何，我关于坚持使用模板的建议仍然很重要。

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