vhdl 中的 process 语句中的顺序执行 [英] sequential execution in process statement in vhdl

问题描述

对于vhdl中的process语句，据说一个process语句内部的执行顺序是顺序的.我的问题是，请先看下面的代码，a、b 和 c 信号是在进程语句中的 if 语句中同时还是按顺序分配给它们的新值?

 process(clk) 是开始如果rising_edge(clk) 那么a <= b ;b <= c ;c <= a;万一;结束过程；

所以如果这是顺序的，我必须说在进程结束后，a 等于 b，b 等于 c，c 等于 b，因为我们在将 a 分配给 c 之前将 b 分配给了 a.然而，这对于硬件来说似乎是不可能的.

解决方案

构建包含流程的最小、完整和可验证示例:

library ieee;使用 ieee.std_logic_1164.all;实体 sequent_exec 是最终实体；sequent_exec 的架构 foo 是信号 a: std_ulogic := '1';信号 b, c: std_ulogic := '0';信号时钟:std_ulogic := '0';开始时钟:过程开始等待 10 ns；clk <= 不是 clk;如果现在 >200 ns 然后等待;万一;结束过程；被测件:进程(时钟)是开始如果rising_edge(clk) 那么a <= b ;b <= c ;c <= a;万一;结束过程；终端架构；

我们将 a、b 和 c 的值从一个移到另一个作为循环移位寄存器:

发生这种情况的原因与 VHDL 的仿真周期的运作方式有关.

参见 IEEE 标准 1076-2008

10.5 简单信号分配(10.5.1 一般):

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信号分配语句修改包含在一个或多个信号的驱动程序中的预计输出波形(见 14.7.2)，为一个或多个信号安排一个力，或安排一个或多个信号的释放(见 14.7.3).

信号分配将新值排队以进行信号更新.10.5.2.2 执行简单赋值语句中描述了如何操作投影输出波形队列:

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对波形元素的评估产生单个事务.事务的时间分量由添加到波形元素中时间表达式值的当前时间确定.对于第一种形式的波形元素，交易的价值分量由波形元素中的价值表达式决定.

没有时间表达式的赋值是当前模拟时间.(将发生增量周期 - 不提前模拟时间的模拟周期).中描述的交易顺序10.5.2.2 告诉我们旧事务到同一模拟时间被删除.

这意味着任何模拟时间只有一个队列条目，并解释了为什么对特定信号的最后分配是导致事务的那个(并为进程敏感的信号生成事件).

14.7 模型的执行包含有关模拟循环如何运作的信息(14.7.5 模型执行).

14.7.5.1 一般:

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模型的执行包括初始化阶段，然后是模型描述中流程语句的重复执行.每一次这样的重复都被称为一个模拟循环.在每个循环中，计算描述中所有信号的值.如果此计算的结果是在给定信号上发生事件，则对该信号敏感的流程语句将恢复并作为仿真周期的一部分执行.

14.7.5.3 模拟周期描述了模拟周期，此处使用 IEEE Std 1076-1993 为简单起见，避免与 VHPI 操作混淆:

12.6.4 模拟周期

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模型的执行包括初始化阶段，然后是模型描述中流程语句的重复执行.每一次这样的重复都被称为一个模拟循环.在每个循环中，计算描述中所有信号的值.如果此计算的结果是在给定信号上发生事件，则对该信号敏感的进程语句将恢复并作为仿真周期的一部分执行.

在初始化开始时，假定当前时间 Tc 为 0 ns.

初始化阶段包括以下步骤:

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-- 计算每个明确声明的信号的驱动值和有效值，并将信号的当前值设置为有效值.假设该值是模拟开始前无限长时间内的信号值.

-- 将 S'Stable(T) 或 S'Quiet(T) 形式的每个隐式信号的值设置为 True.S'Delayed(T) 形式的每个隐式信号的值被设置为其前缀 S 的初始值.

-- 每个隐式 GUARD 信号的值设置为评估相应保护表达式的结果.

-- 模型中的每个非延迟进程都会执行，直到它挂起.

-- 模型中的每个延迟过程都会执行，直到它挂起.

-- 下一个仿真周期(在本例中为第一个仿真周期)的时间 Tn 根据仿真周期步骤 f 的规则计算，如下所示.

一个模拟周期包括以下步骤:

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一个.当前时间 Tc 设置为等于 Tn.当 Tn= TIME'HIGH 并且在 Tn 处没有活动驱动程序或进程恢复时，模拟完成.
湾更新模型中的每个活动显式信号.(结果可能会在信号上发生事件.)
C.更新模型中的每个隐式信号.(结果可能会在信号上发生事件.)
d.对于每个进程 P，如果 P 当前对信号 S 敏感，并且如果在此模拟周期中 S 上发生了事件，则 P 继续运行.
e.在当前模拟周期中恢复的每个非延迟进程都会执行，直到它挂起.
F.下一个模拟周期的时间 ​​Tn 是通过将其设置为

中的最早时间来确定的<块引用>

1. TIME'HIGH，
2. 下一次驱动程序变为活动状态，或
3. 下一次进程恢复的时间.
4. 如果 Tn = Tc，则下一个模拟周期(如果有)将是一个增量周期.

g.如果下一个仿真周期是增量周期，则跳过此步骤的其余部分.否则，每个已恢复但自上次恢复后尚未执行的延迟进程将一直执行，直到它挂起.然后根据步骤 f 的规则重新计算 Tn.如果任何延迟过程的执行导致在当前模拟周期之后立即发生增量周期，则这是一个错误.

信号值在流程执行期间不会改变.它们的更新被排队并应用在模拟周期执行的不同步骤中.

回到 -2008 年:

10. 顺序陈述，10.1 总则

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本节描述了各种形式的顺序语句.顺序语句用于定义执行子程序或进程的算法；它们按照出现的顺序执行.

我们看到顺序信号分配执行的顺序与信号更新的顺序无关.

for process statement in vhdl, it is said that the order of execution inside a process statement is sequential. My question is that, please look at the code below first, are a, b and c signals assigned to their new values concurrently or sequentially in if statement which is in process statement?

   process(clk) is
   begin
   if rising_edge(clk) then
   a <= b ;
   b <= c ;
   c <= a;
   end if;
   end process;

So if this is sequential, I must say that after the end of process, a is equal to b, b is equal to c and c is equal to b because we assigned b to a before we assigned a to c. However, this does seem not possible for hardware to do.

解决方案

Constructing a Minimal, Complete, and Verifiable example containing your process:

library ieee;
use ieee.std_logic_1164.all;

entity sequent_exec is
end entity;

architecture foo of sequent_exec is
    signal a:       std_ulogic := '1';
    signal b, c:    std_ulogic := '0';
    signal clk:     std_ulogic := '0';
begin
    CLOCK:
    process
    begin
        wait for 10 ns;
        clk <= not clk;
        if now > 200 ns then
            wait;
        end if;
    end process;
DUT:
    process(clk) is
    begin
    if rising_edge(clk) then
    a <= b ;
    b <= c ;
    c <= a;
    end if;
    end process;
end architecture;

We see a, b and c shift values from one to another as a recirculating shift register:

Why that occurs is do to how VHDL's simulation cycle operates.

See IEEE Std 1076-2008

10.5 Simple Signal assignments (10.5.1 General):

A signal assignment statement modifies the projected output waveforms contained in the drivers of one or more signals (see 14.7.2), schedules a force for one or more signals, or schedules release of one or more signals (see 14.7.3).

A signal assignment queues a new value for signal update. How the projected output waveform queue is operated is described in 10.5.2.2 Executing a simple assignment statement:

Evaluation of a waveform element produces a single transaction. The time component of the transaction is determined by the current time added to the value of the time expression in the waveform element. For the first form of waveform element, the value component of the transaction is determined by the value expression in the waveform element.

An assignment without a time expression is to the current simulation time. (A delta cycle will occur - a simulation cycle without advancing the simulation time). The sequence of transactions described in 10.5.2.2 tell us old transactions to the same simulation time are deleted.

This means there's only one queue entry for any simulation time and explains why the last assignment to a particular signal is the one resulting in a transaction (and producing an event for a signal a process is sensitive to).

14.7 Execution of a model contains information about how a simulation cycle operates (14.7.5 Model execution).

14.7.5.1 General:

The execution of a model consists of an initialization phase followed by the repetitive execution of process statements in the description of that model. Each such repetition is said to be a simulation cycle. In each cycle, the values of all signals in the description are computed. If as a result of this computation an event occurs on a given signal, process statements that are sensitive to that signal will resume and will be executed as part of the simulation cycle.

14.7.5.3 Simulation cycle describes the simulation cycle, the IEEE Std 1076-1993 is used here for simplicity not being cluttered with VHPI actions:

12.6.4 The simulation cycle

The execution of a model consists of an initialization phase followed by the repetitive execution of process statements in the description of that model. Each such repetition is said to be a simulation cycle. In each cycle, the values of all signals in the description are computed. If as a result of this computation an event occurs on a given signal, process statements that are sensitive to that signal will resume and will be executed as part of the simulation cycle.

At the beginning of initialization, the current time, Tc, is assumed to be 0 ns.

The initialization phase consists of the following steps:

-- The driving value and the effective value of each explicitly declared signal are computed, and the current value of the signal is set to the effective value. This value is assumed to have been the value of the signal for an infinite length of time prior to the start of simulation.

-- The value of each implicit signal of the form S'Stable(T) or S'Quiet(T)is set to True. The value of each implicit signal of the form S'Delayed(T) is set to the initial value of its prefix, S.

-- The value of each implicit GUARD signal is set to the result of evaluating the corresponding guard expression.

-- Each nonpostponed process in the model is executed until it suspends.

-- Each postponed process in the model is executed until it suspends.

-- The time of the next simulation cycle (which in this case is the first simulation cycle), Tn, is calculated according to the rules of step f of the simulation cycle, below.

A simulation cycle consists of the following steps:

a. The current time, Tc is set equal to Tn. Simulation is complete when Tn= TIME'HIGH and there are no active drivers or process resumptions at Tn.
b. Each active explicit signal in the model is updated. (Events may occur on signals as a result.)
c. Each implicit signal in the model is updated. (Events may occur on signals as a result.)
d. For each process P, if P is currently sensitive to a signal S and if an event has occurred on S in this simulation cycle, then P resumes.
e. Each nonpostponed process that has resumed in the current simulation cycle is executed until it suspends.
f. The time of the next simulation cycle, Tn, is determined by setting it to the earliest of

1. TIME'HIGH,
2. The next time at which a driver becomes active, or
3. The next time at which a process resumes.
4. If Tn = Tc, then the next simulation cycle (if any) will be a delta cycle.

g. If the next simulation cycle will be a delta cycle, the remainder of this step is skipped. Otherwise, each postponed process that has resumed but has not been executed since its last resumption is executed until it suspends. Then Tn is recalculated according to the rules of step f. It is an error if the execution of any postponed process causes a delta cycle to occur immediately after the current simulation cycle.

Signal values don't change during the execution of a process. Their updates are queued and applied in a different step in the execution of a simulation cycle.

back to -2008:

10. Sequential statements, 10.1 General

The various forms of sequential statements are described in this clause. Sequential statements are used to define algorithms for the execution of a subprogram or process; they execute in the order in which they appear.

We see the order of sequential signal assignment execution doesn't relate to the order signals are updated.

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