将泛型传递给记录端口类型 [英] Passing Generics to Record Port Types

问题描述

我最近确实开始为我的端口定义使用记录，特别是如果我想对属于某个接口的信号进行分组.但是，我在这里面临的问题是我无法通过泛型将 std_logic_vector 的宽度传递给实体.所以我基本上想做的是以下内容:

I did recently start to use records for my port definitions, especially if I want to group signals that belong to a certain interface. However, the problem I'm facing here is that I cannot pass, say the width of a std_logic_vector, to the entity by means of a generic. So what I basically want to do is the following:

library ieee;
use ieee.std_logic_1164.all;
use work.math_pkg.all;

package fifo_pkg is

  type fifo_in_type is record
    data_in : std_logic_vector(DATA_WIDTH_??- 1 downto 0);
    rd      : std_logic;
    wr      : std_logic;
  end record;

  type fifo_out_type is record
    data_out : std_logic_vector(DATA_WIDTH_?? - 1 downto 0);
    empty    : std_logic;
    full     : std_logic;
  end record;

  component fifo is
    generic
      (
        MIN_DEPTH  : integer;
        DATA_WIDTH : integer
        );
    port
      (
        clk   : in  std_logic;
        res_n : in  std_logic;
        i     : in  fifo_in_type;
        o     : out fifo_out_type
        );
  end component fifo;

end fifo_pkg;   

所以理想的解决方案是我可以在我的记录中使用与实体中相同的泛型.(因此 DATA_WIDTH 与 DATA_WIDTH_ 相同??).我知道这应该可以与 vhdl 2008 配合使用，但是我的 quartus II 11sp1 不支持记录中的泛型.

So the ideal solutions would be when i can use the same generic in my record as i did in the entity. (So that DATA_WIDTH is the same as DATA_WIDTH_??). I know that this should work somehow with vhdl 2008, however my quartus II 11sp1 does not support generics in records.

有没有一种优雅的方式来实现这种可合成的通用传递"?我知道一个人可以只在包中存储一个常量，但是我不能使用同一个 fifo 包来实例化几个不同宽度的 fifo.

Is there an elegant way to achieve that kind of "generic passing" that is synthesizable? I know that one could just store a constant in the package, but then I cannot use the same fifo package to instantiate several fifo's with different widths.

谢谢一百万，

推荐答案

Quartus 可以使用类型泛型吗?

Can you use type generics with Quartus?

然后您完全不指定类型，以便您可以创建 integers 或任何其他数据类型的 FIFO:

Then you leave the type completely unspecified, so that you can create a FIFO of integers or any other data type:

package fifo_pkg is
  generic (type element_type);

  type fifo_in_type is record
    data_in : element_type;
    rd      : std_logic;
    wr      : std_logic;
  end record;

  type fifo_out_type is record
    data_out : element_type;
    empty    : std_logic;
    full     : std_logic;
  end record;

  component fifo is
    generic
      (
        MIN_DEPTH  : integer;
        DATA_WIDTH : integer
        );
    port
      (
        clk   : in  std_logic;
        res_n : in  std_logic;
        i     : in  fifo_in_type;
        o     : out fifo_out_type
        );
  end component fifo;

end fifo_pkg;

然后当你想使用它时:

package wide_fifo_pkg is new fifo_pkg
   generic map (type => std_logic_vector(31 downto 0));

然后你可以使用fifo_in_type和fifo_out_type:

signal i : fifo_in_type;

如果您在一个设计单元中有多个 FIFO，您可以创建多个版本的包并使用包前缀来获得正确的类型:

If you have more than one FIFO in a design unit you can create several versions of the package and use the package prefix to get the right type:

package narrow_fifo_pkg is new fifo_pkg
   generic map (type => std_logic_vector(3 downto 0));

signal i32 : wide_fifo_pkg.fifo_in_type;
signal i4  : narrow_fifo_pkg.fifo_in_type;

<小时>

另一个 VHDL 2008 选项:您可以拥有不受约束的记录类型:

---

Another VHDL 2008 option: you can have an unconstrained record type:

 type fifo_in_type is record
    data_in : std_logic_vector;
    rd      : std_logic;
    wr      : std_logic;
  end record;

然后您可以为您的各种用途创建子类型:

which you can then create subtypes of for your various uses:

subtype fifo1_data_type is fifo_in_type(data_in(31 downto 0));
subtype fifo2_data_type is fifo_in_type(data_in(15 downto 0));

<小时>

不知道 Quartus 是否支持这些选项中的任何一个 - 请告诉我们！

---

No idea if Quartus supports either of those options - please let us know!

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