wait 语句必须包含带有 UNTIL 关键字的条件子句 [英] wait statement must contain condition clause with UNTIL keyword

问题描述

以下 VHDL 将用于测试台架.在分析过程中，我在第一个等待语句上不断收到错误:等待语句必须包含带有 UNTIL 关键字的条件子句"我有几个以这种方式编写的工作测试台.我似乎无法找到错误可能是什么.

The following VHDL is to be used to test bench. I keep getting an error on the first wait statement during analysis : "wait statement must contain condition clause with UNTIL keyword" I have several working test benches written this way. I can't seem to find what the error might be.

`library IEEE;
USE IEEE.std_logic_1164.all;
entity case_ex_TB is end;
architecture simple_test of case_ex_TB is
--- DUT Component Declaration ---
component case_ex
    port(
    clk, rstN: IN std_logic;
    color: OUT std_logic_vector(2 downto 0));
end component;
--- Signals Declaration ---
signal rst, clock: std_logic:='0';
signal color: std_logic_vector(2 downto 0);

begin
DUT: case_ex  --- DUT instantiation ---
port map (clk => clock,
         rstN => rst,
         color => color);
--- Signal's Waves Creation ---
rst <= '1','0' after 50 ns, '1' after 2 us;
clock_crtate: process
begin
    while rst = '0' loop
        clock <= '1','0' after 50 ns;
        wait for 100 ns;
    end loop;
        clock <= '1';
        wait;
end process;
end simple_test;`

推荐答案

您收到此错误是因为您已将测试平台设置为 Quartus-II 中的顶级实体.顶层实体必须保持组件case_ex，并且该组件必须包含可合成的代码.

You get this error because you have set your testbench as the top-level entity in Quartus-II. The top-level entity must remain the component case_ex, and this component must contain synthesizable code.

要模拟您的测试平台，您必须配置一个测试平台.只需点击RTL 模拟"之前的加号，然后点击编辑设置".(名称可能因 Quartus 版本而异).

To simulate your testbench, you must configure a testbench. Just klick on the plus-sign before "RTL Simulation" and then "Edit Settings". (Names may differ with Quartus version).

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