从 VHDL 代码生成状态机图? [英] Generate State Machine graph from VHDL code?
本文介绍了从 VHDL 代码生成状态机图?的处理方法，对大家解决问题具有一定的参考价值，需要的朋友们下面随着小编来一起学习吧！
问题描述
有没有很好的工具可以从 VHDL 代码生成状态机图?我正在使用赛灵思 ISE Webpack.干杯！
Is there any quite good tool to generate State Machine graph from VHDL code? I'm using Xilinx ISE Webpack. Cheers!
推荐答案
Active HDL 有一个功能称为Code2Graphics"，支持这一点.此外，一些综合工具(通常是您需要付费购买的工具)也支持这一点.
Active HDL has a feature called "Code2Graphics" which supports this. Additionally, some synthesis tools (typically ones you would have to pay for) also support this.
请注意，RTL 视图在综合工具(例如 XST)中更常见.
Note that an RTL view is more commonly available in synthesis tools (such as XST).
这篇关于从 VHDL 代码生成状态机图?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
查看全文
