信号x无法合成,同步描述不好 [英] Signal x cannot be synthesized, bad synchrononous description
问题描述
我对 vhdl 很陌生,我无法找到导致此错误的原因.我正在尝试复制 CD54/74HC192 电路的功能.
I'm very new to vhdl and i cannot manage to find what's causing this error. I'm trying to replicate the functionality of a CD54/74HC192 Circuit.
任何帮助将不胜感激.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity upg1 is
Port ( clock_up : in std_logic;
clock_down : in std_logic;
reset : in STD_LOGIC;
asyn_load : in STD_LOGIC;
bcd_in : in STD_LOGIC_VECTOR (3 downto 0);
bcd_ut : out STD_LOGIC_VECTOR (3 downto 0);
term_up : out STD_LOGIC;
term_down : out STD_LOGIC);
end upg1;
architecture Behavioral of upg1 is
subtype state_type is integer range 0 to 15;
signal next_state, present_state: state_type;
signal clock : std_logic;
begin
process(clock_up, clock_down)
begin
if clock_up = '1' then
clock <= clock_down;
else
if clock_down = '1' then
clock <= clock_up;
end if;
end if;
end process;
process(present_state, asyn_load, clock) -- line 65
begin
if reset= '1' then
next_state <= 0;
end if;
if (asyn_load = '1' and (rising_edge(clock))) then
if present_state = 9 or present_state = 13 or present_state = 15 then
present_state <= 0;
elsif
present_state = 10 or present_state = 12 or present_state = 14 then
present_state <= 9;
elsif
present_state = 11 then
present_state <= 4;
else
present_state <= present_state + 1;
end if;
else
if rising_edge(clock) then
if present_state = 12 then
present_state <= 3;
elsif present_state = 13 then
present_state <= 4;
elsif present_state = 14 then
present_state <= 5;
elsif present_state = 15 then
present_state <= 6;
elsif present_state = 0 then
present_state <= 9;
else
present_state <= present_state - 1;
end if;
else
present_state <= TO_INTEGER(UNSIGNED(bcd_in));
end if;
end if;
end process;
end Behavioral;
我尝试了不同的方法来解决错误,但无法解决.
I've tried different methods in resolving the error but unable to do so.
错误控制台:
line 65: Signal present_state cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.)
推荐答案
首先,不要同时使用 numeric_std
和 std_logic_arith/unsigned
包,而只使用 numeric_std
因为这是一个 VHDL 标准包,其中 std_logic_arith/unsigned
是 Synopsys 专有的.所以改为:
First, don't use both packages numeric_std
and std_logic_arith/unsigned
, but use only numeric_std
since this is a VHDL standard package, where std_logic_arith/unsigned
are Synopsys proprietary. So change to:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
关于真正的问题,然后使用如下结构通过触发器在 VHDL 中创建状态:
About the real issue, then create state in VHDL through flip-flops using a structure like:
process(clock, reset)
begin
if rising_edge(clock) then
...
end if;
if reset = '1' then
...
end if;
end if;
Synthesis 将识别出这一点并推断出触发器.reset
和 clock
不应在进程内的其他地方使用.
Synthesis will recognize this and infer flip-flops. The reset
and clock
should not be used elsewhere inside the process.
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