AMD64 页条目基地址字段如何以 40 位编码 52 位地址? [英] How do AMD64 page entry base address fields encode a 52-bit address in 40 bits?

问题描述

我正在尝试手动遍历分页结构，以便将虚拟地址转换为其物理地址.我有一个关于存储在 PML4E、PDPE、PDE 和 PTE 中的物理基地址字段的问题.我系统上的页面大小是 4KB.我在内核模式下在 Windows 上执行此操作.

I'm trying to manually walk the paging structures in order to convert a virtual address into its physical address. I have a question about the physical base address fields stored in the PML4E, PDPE, PDE, and PTE. The page size on my system is 4KB. I'm doing this on Windows in kernel mode.

正如 amd64 手册所说，cr3 的第 51-12 位包含 PML4 的物理基址.然而，它说第 11-0 位应该被假定为 0.我想知道是否同样的事情适用于其他分页结构的基地址字段，因为描述转换过程的图表说 52，但实际大小是仅 40(位 51-12).

As the amd64 manual says, bits 51-12 of cr3 contain the physical base address of the PML4. However, it says that bits 11-0 should be assumed as 0. I was wondering if the same thing applies to the base address fields of the other paging structures, because the diagrams that describe the translation process says 52, however the actual size is just 40 (bits 51-12).

我如何在 C 中进行翻译的示例:

Sample of how I'm doing the translation in C:

// clear out everything except base address field
ULONG_PTR pPml4 = __readcr3() & ~0xFFF0000000000FFF,
    dataEntry;

copyAddress.PhysicalAddress.QuadPart = pPml4 + (sourceAddress.Hard.PageMapLevel4Index * 8);

if (MmCopyMemory(&dataEntry, copyAddress, 8, MM_COPY_MEMORY_PHYSICAL, &trans) != STATUS_SUCCESS) {
    ...
}

// dataEntry now has correct PML4E

// clear out everything except base address field
dataEntry &= ~0xFFF0000000000FFF;

// do I skip this?
dataEntry >>= 12;

推荐答案

来自手册的第 5.4 节:

From section 5.4 of the manual:

翻译表基地址字段.转换表基地址字段指向页转换层次结构中下一个较低级别表的物理基地址.页面数据结构表总是在 4 KB 边界上对齐，因此只有位 11 以上的地址位是存储在转换表基地址字段中.位 11:0 假定为 0.字段的大小取决于模式...

Translation-Table Base Address Field. The translation-table base-address field points to the physical base address of the next-lower-level table in the page-translation hierarchy. Page datastructure tables are always aligned on 4-Kbyte boundaries, so only the address bits above bit 11 are stored in the translation-table base-address field. Bits 11:0 are assumed to be 0. The size of the field depends on the mode...

所以是的，低 12 位是 0 以构成 52 位物理地址.

So yes, the low 12 bits are 0 to make a 52-bit physical address.

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