为什么在 x86-64 中，虚拟地址比物理地址短 4 位(48 位对 52 位)? [英] Why in x86-64 the virtual address are 4 bits shorter than physical (48 bits vs. 52 long)?
问题描述
在低级编程:英特尔® 64 位架构上的 C、汇编和程序执行"一书中，我读到:
<块引用>每个虚拟 64 位地址(例如，我们在程序中使用的地址)由几个字段组成.地址本身实际上只有 48 位宽的;它被符号扩展为 64 位规范地址.它的特点是它的左17位是相等的.如果条件是不满意，地址在使用时立即被拒绝.然后48 位虚拟地址转换为 52 位物理地址在特殊表的帮助下寻址.
为什么虚拟地址和物理地址相差4位?
我相信你在谈论 x86-64，我的回答是基于该架构.
<小时>在 64 位模式下运行时，CPU 使用改进的功能将虚拟地址转换为物理地址，称为
所有这些表背后的基本原理是稀疏:用于将虚拟地址转换为物理地址的元数据是巨大的 - 如果我们只使用 4KiB 页面，我们将需要 264 - 12 = 252 个条目以覆盖整个 64 位地址空间.
表允许采用稀疏方法，只在内存中填充必要的条目.
这种设计反映在虚拟地址的划分方式上(因此，间接地体现在级别数上)，仅使用 9 位运行来对每个级别的表进行索引.
从包含的第 12 位开始，这给出:级别 1 -> 12-20，级别 2 -> 21-29，级别 3 -> 30-38，级别 4 -> 39-47.
这解释了目前只有 48 位虚拟地址空间的实现限制.
请注意，在使用逻辑地址的指令级别，我们完全支持 64 位地址.
分段级别也提供全面支持，该部分将逻辑地址转换为线性地址.
所以限制来自PAE.
我个人的观点是，AMD 急于率先推出支持 64 位的 x86 CPU，并重新使用了 PAE，并使用新的间接级别对其进行了修补以将其转换为 48 位.
请注意，Intel 和 AMD 都允许未来的实现使用 64 位作为虚拟地址(可能有更多的表).
但是，两家公司都为物理地址设置了 52 位的硬限制.为什么?
答案仍然可以在分页的工作原理中找到.
在 32 位模式下，每个表中的每个条目都是 32 位宽；低位用作标志(因为对齐要求使它们对转换过程无用)但高位全部用于转换，从而提供 32/32 虚拟/物理转换.
重要的是要强调所有 32 位都被使用了，而一些较低的位没有用作标志，英特尔将它们标记为忽略"或可用"，这意味着操作系统可以自由使用它们.
当英特尔推出 PAE 时，他们需要多 4 位(当时 PAE 是 36 位)，合乎逻辑的做法是将每个条目的大小加倍，因为这样可以创建比例如，40 位表项.
这为英特尔提供了大量备用空间，他们将其标记为保留(在旧版本的英特尔 SDM 手册中可以更好地观察到这一点，
它表明 64 位物理地址是不可能的(对于大页面，仍然有办法解决这个问题，但考虑到位的布局似乎不太可能)但没有解释为什么 AMD 将限制设置为 52位.
嗯，这很难说.
当然，物理地址空间的大小与一些硬件相关:更多的管脚(尽管使用集成内存控制器，但随着 DDR 规范多路复用大量信号而减轻)和更多空间在缓存/TLB 中.
在这个问题(类似但还不够，使其成为重复)一个答案城市维基百科，据称又引用了 AMD，声称 AMD 的工程师在适当考虑收益和成本后将限制设置为 52 位.
我分享了什么Hans Passant 6 多年前写道:当前的分页机制不适合完整的 64 位物理寻址，这可能是 Intel 和 AMD 从不费心保留每个条目中的高位保留的原因.
两家公司都知道，随着技术接近 52 位限制，它也将与实际形式大不相同.
到那时，他们通常会设计出更好的内存机制，从而避免对现有机制进行过度设计.
In the book "Low-Level Programming: C, Assembly, and Program Execution on Intel® 64 Architecture" I read:
Each virtual 64-bit address (e.g., ones we are using in our programs) consists of several fields. The address itself is in fact only 48 bits wide; it is sign-extended to a 64-bit canonical address. Its characteristic is that its 17 left bits are equal. If the condition is not satisfied, the address gets rejected immediately when used. Then 48 bits of virtual address are transformed into 52 bits of physical address with the help of special tables.
Why is the difference in 4 bits between the virtual address and the physical address?
I believe you are talking about x86-64, my answer is based on that architecture.
When operating in 64-bit mode the CPU uses a revamped feature to translate virtual addresses into physical addresses known as PAE - Physical address extension.
Originally invented to break the 4GiB limit while still using 32-bit pointers, this feature involves the use of 4 level of tables.
Each table gives a pointer to the next table, down to the rightmost one that gives the upper bits of physical address. To get an idea look at this picture from the AMD64 Architecture Programming Manual:
The rationale behind all those tables is sparsity: the metadata for translating virtual addresses into physical addresses is huge - if we were to use 4KiB pages only we'd need 264 - 12 = 252 entries to cover the whole 64-bit address space.
Tables allow for a sparse approach, only the entries necessary are populated in memory.
This design is reflected in how the virtual address is divided (and thus, indirectly, in the number of levels), only runs of 9 bits are used to index the tables at each level.
Starting from bit 12 included, this gives: level 1 -> 12-20, level 2 -> 21-29, level 3 -> 30-38, level 4 -> 39-47.
This explains the current implementation limit of only 48 bits of virtual address space.
Note that at the instruction level, where logical addresses are used, we have full support for 64 bits addresses.
Full support is also available at the segmentation level, the part that translates logical addresses into linear addresses.
So the limitation comes from PAE.
My personal opinion is that AMD rushed to be the first to ship an x86 CPU with 64-bit support and reused PAE, patching it with a new level of indirection to translate up to 48 bits.
Note that both Intel and AMD allow a future implementation to use 64 bits for the virtual address (probably with more tables).
However, both companies set a hard limit of 52 bit for the physical address. Why?
The answer can still be found in how paging work.
In 32-bit mode, each entry in each table is 32 bits wide; the low bits are used as flags (since the alignment requirements make them useless for the translation process) but the higher bits were all used for the translation, giving a 32/32 virtual/physical translation.
It's important to stress out that all the 32 bits were used, while some of the lower bits were not used as flags, Intel marked them as "Ignored" or "Available" meaning with that that the OS was free to use them.
When Intel introduced PAE, they needed 4 more bits (PAE was 36 bits back then) and the logical thing to do was to double the size of each entry since this creates a more efficient layout than a, say, 40-bit table entry.
This gave Intel a lot of spare space and they marked it as reserved (This can be better observed in older versions of the Intel SDM manuals, like this one).
With time, new attributes were needed in an entry, the most famous one being the XD/NX bit.
Protection keys are also a, relatively new, feature that takes space in an entry.
This shows that a full 64/64 bits virtual/physical translation is not possible anymore with the current ISA.
For a visual reference, here is the format of the 64-bit PAE table entries:
It shows that a 64-bit physical address is not possible (for huge pages there still is a way to fix this but given the layout of the bits that seems unlikely) but doesn't explain why AMD set the limit to 52 bits.
Well, it's hard to say.
Certainly, the size of the physical address space has some hardware cost associated with it: more pins (though with the integrated memory controller, this is mitigated as the DDR specs multiplex a lot of signals) and more space in the caches/TLBs.
In this question (similar but not enough make this a duplicate) an answer cities Wikipedia, that in turn allegedly cites AMD, claiming that AMD's engineers set the limit to 52 bits after due considerations of benefits and costs.
I share what Hans Passant wrote more than 6 years ago: the current paging mechanisms are not suitable for a full 64-bit physical addressing and that's probably the reason why both Intel and AMD never bothered keeping the high bits in each entry reserved.
Both companies know that as the technology will approach the 52-bit limit it will also be very different from its actual form.
By the time they will have designed a better mechanism for memory in general, so they avoided over-engineering the existing one.
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