ARM 指令集中的缩写(Rn, Rd, ...)是什么意思? [英] What do the abbriviations (Rn, Rd, ...) in the instruction set of ARM mean?

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问题描述

最近我检查了 ARM Cortex-M3 处理器的指令集.例如:

ADD 

这些缩写到底是什么意思?我猜他们的意思是不同类型的地址,比如直接寻址、相对寻址等等.但究竟是什么?

谢谢!

解决方案

基础:

  • Rd 是目的地,RnRm 是来源.它们都是通用的整数寄存器;FP 将使用 Sd/Sn/SmDd/Dn/Dm 单人或双人.
    ARM 语法将目标放在左侧,在只读源操作数之前.

有关更多信息,请参阅 Notlikethat 的答案.一些小的补充:

  • t:在 这篇文章,一位 ARM 员工评论说t"可能意味着转移"而不是目标".

    由于 t 通常出现在 LDR 和 STR 等内存指令中,我理解这意味着转移到/从内存",例如在 ARMARMv8-fa 上:

    LDR , [, (|){, {<金额>}}]STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend>{<金额>}}]

    其中 t 是内存读取和写入的源/目标.

    这在 STR 和 LDXR 指令寄存器的描述中也有进一步的建议:

    <块引用>

    是要传输的通用寄存器的 64 位名称,编码在Rt"中领域.

    但是 LDR 指令显示已加载":

    <块引用>

    是要加载的通用寄存器的 64 位名称,编码在Rt"中领域.

    这个术语特别有意义,因为 ARM 是 RISC-y,所以执行内存 IO 的指令相对较少,而且他们倾向于这样做(不像 x86 中常见的添加和存储到内存).

  • t1t2:它们用于一次加载/存储两个值的内存指令,例如ARMv8 LDP/STP:

    LDP 、[]、#STP<Xt1>、<Xt2>、[<Xn|SP>、#<imm>]!

  • nm 只是数学中常用的整数变量/索引名称

  • s:

    • STXR 指令将 Xt(如 STR)存储到内存中,但它还会获得第二个返回值(写入成功)到 Ws:

      STXR , , [{,#0}]

      所以大概选择 s 是因为它在 t 之前,就像 mn 之前一样.

    • 某些 ARMv7/aarch32 指令可以在寄存器中进行移位,Rs 是该寄存器的名称,例如:

      ORR{}{} {,} , , <Rs>

      我无法轻松找到 aarch64.

  • 如果有记录,C2 章关于 A64 指令描述"可能是提供信息的好位置,但它不在那里

recently i checked the Instruction Set for an ARM Cortex-M3 processor. For example:

ADD <Rd>, <Rn>, <Rm>

What do those abbriviations mean exactly? I guess they mean different kinds of addresses, like directely addressed, relatively addressed or so. But what exactly?

Thanks!

解决方案

Basics:

  • Rd is the destination, Rn and Rm are sources. They're all general-purpose integer registers; FP would use Sd / Sn / Sm or Dd / Dn / Dm for single or double.
    ARM syntax puts the destination(s) on the left, before read-only source operands.

See Notlikethat's answer for more. Some small additions to that:

  • t: in this post, an ARM employee comments that "t" might mean "transfer" instead of "target".

    Since t generally appears in memory instructions like LDR and STR, I understand that that means "transfer to/from memory", e.g. on ARMARMv8-fa:

    LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
    STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
    

    where the t is the source/destination of memory reads and writes.

    This is also further suggested in the description of the STR and LDXR instruction registers:

    <Xt> Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

    The LDR instruction however says "loaded":

    <Xt> Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

    This terminology is especially meaningful because ARM is RISC-y and so there are relatively few instructions that do memory IO, and they tend to do just that (unlike say add and store to memory as is common in x86).

  • t1 and t2: these are used for memory instructions that load/store two values at once, e.g. the ARMv8 LDP/STP:

    LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
    STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
    

  • n and m are just commonly used integer variable/index names in mathematics

  • s:

    • the STXR instruction stores to memory fom Xt (like STR), but it also gets a second return value (did the write succeed) to Ws:

      STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]
      

      so presumably s was chosen because it comes before t like m comes before n.

    • Some ARMv7/aarch32 instructions could take a shift in a register, and Rs is the name given to that register, e.g.:

      ORR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> 
      

      I couldn't easily find aarch64 ones.

  • if it were documented, "Chapter C2 About the A64 Instruction Descriptions" might have been a good location for the information, but it's not there

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