当前 CPU 上的分支预测有多普遍? [英] How prevalent is branch prediction on current CPUs?

问题描述

由于对性能的巨大影响，我从不怀疑我今天的桌面 CPU 是否有分支预测.当然可以.但是各种 ARM 产品又如何呢?iPhone 或 android 手机有分支预测吗?较旧的任天堂 DS?基于 PowerPC 的 Wii 怎么样?PS 3?

Due to the huge impact on performance, I never wonder if my current day desktop CPU has branch prediction. Of course it does. But how about the various ARM offerings? Does iPhone or android phones have branch prediction? The older Nintendo DS? How about PowerPC based Wii? PS 3?

他们是否有一个复杂的预测单元并不那么重要，但他们是否至少有一些动态预测，以及他们是否按照预期执行一些指令分支.

Whether they have a complex prediction unit is not so important, but if they have at least some dynamic prediction, and whether they do some execution of instructions following an expected branch.

具有分支预测功能的 CPU 的截止时间是多少?几十年前的手持计算器显然没有，而我的台式机有.但是谁能更清楚地勾勒出可以期待动态分支预测的地方?

What is the cutoff for CPUs with branch prediction? A hand held calculator from decades ago obviously doesn't have one, while my desktop does. But can anyone more clearly outline where one can expect dynamic branch prediction?

如果不清楚，我说的是条件变化的预测类型，在运行时改变预期路径.

If it is unclear, I am talking about the kind of prediction where the condition is changing, varying the expected path during runtime.

推荐答案

任何具有超过几个阶段的流水线的 CPU 都至少需要一些原始分支预测，否则它会停止等待计算结果以决定走哪条路.Intel Atom 是一个有序内核，但具有相当深的管道，因此它需要一个相当不错的分支预测器.

Any CPU with a pipeline beyond a few stages requires at least some primitive branch prediction, otherwise it can stall waiting on computation results in order to decide which way to go. The Intel Atom is an in-order core, but with a fairly deep pipeline, and it therefore requires a pretty decent branch predictor.

旧的 ARM 7 设计只有三个阶段.将其与诸如分支延迟槽(MIPS 上需要，SPARC 上可选)之类的东西结合起来，分支预测就没有那么有用了.

Old ARM 7 designs were only three stages. Combine that with things like branch delay slots (required on MIPS, optional on SPARC), and branch prediction isn't so useful.

顺便说一下，当 MIPS 决定通过超越 4 个流水线阶段来获得更高的性能时，分支延迟槽就成了一个烦恼.在最初的设计中，这是必要的，因为没有分支预测器.因此，您必须在分支之前要执行的最后一条指令之前对分支指令进行排序.对于更长的管道，他们需要一个分支预测器，从而避免对分支延迟槽的需求，但他们无论如何都必须模拟它以运行旧代码.

Incidentally, when MIPS decided to get more performance by going beyond 4 pipeline stages, the branch delay slot became an annoyance. In the original design, it was necessary, because there was no branch predictor. Therefore, you had to sequence your branch instruction prior to the last instruction to be executed before the branch. With the longer pipeline, they needed a branch predictor, obviating the need for a branch delay slot, but they had to emulate it anyway in order to run older code.

分支延迟槽的问题在于它只能在大约 50% 的时间内填充有用的指令.剩下的时间，你要么用一条结果可能会被丢弃的指令填充它，要么使用 NO-OP.

The problem with a branch delay slot is that it can only be filled with a useful instruction about 50% of the time. The rest of the time, you either fill it with an instruction whose result is likely to be thrown away, or you use a NO-OP.

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