中断，指令指针和指令队列8086 [英] Interrupts, Instruction Pointer, and Instruction Queue in 8086

问题描述

假设一个外部中断请求到8086的处理器作出正在执行（如果有的话）在完成当前指令之后将处理该中断。处理中断之前，程序的状态也将通过将数据推入堆栈段保存（PSW标志，寄存器等）。

Suppose an external interrupt request is made to 8086. Processor will handle the interrupt after completing the current instruction being executed (if any). Before handling of the interrupt, the state of the program will also be saved (PSW flag, registers etc.) by pushing data onto the stack segment.

现在，大多数的教程/文档描述了指令指针也被压入堆栈段，这是好的，因为它指向了code段（被做了中断请求之前）指令的下一个字节。

Now, most tutorials/documents describe that instruction pointer is also pushed onto the stack segment, which is okay because it was pointing to the next byte of instruction in the code segment (just before interrupt request was made).

但发生了什么指令队列？难道它也压入堆栈段时中断请求被处理？或者是它的内容被清零？在这种情况下，不应该指令指针被递减，以便它可以制成指向回在code段中的previous指令（中断已送达后）

But what happens to the instruction queue? Is it also pushed onto the stack segment when an interrupt request is being handled? Or is it that its contents are cleared to zero? In this case, shouldn't the instruction pointer be decremented so that it can be made to point back to the previous instructions in the code segment (after interrupt has been served)?

在这里， 中断请求后的其实就是中断请求已送达的之后的。这是什么图显示的是，中断请求来之前，该指令是缓存，与IP指向指令的下一个字节在CS内存段的地址。为了更好地服务中断请求，寄存器的内容（的含IP和标志的）被压入堆栈段。请求送达后，previous内容被装回 - 与IP仍然指向到第7个字节的位置（指令），用队列（缓存）是空的。这是我的疑问是什么。的为IP递减到指回至i1 的？其次，我们需要手动处理的IP（如，将其推到在中断堆栈），或在不中断服务例程处理此我们呢？请，任何帮助是AP preciated，谢谢！

Here, After interrupt request actually means After interrupt request has been served. What this diagram shows is that before interrupt request came, the instructions were cached, with IP pointing to the address of the next byte of instruction in the CS memory segment. To serve the interrupt request, the contents of registers (incl. IP and flags) are pushed onto the stack segment. After request is served, the previous contents are loaded back - with IP still pointing to the location of the 7th byte (of instruction), with queue (cache) being empty. This is what my doubt is. Is IP decremented to point back to i1? Secondly, do we need to manually handle the IP (like, push it onto the stack upon interrupt) or does the interrupt-service-routine handles this for us? Please, any help is appreciated, thanks!

请注意：指令队列 - 8086架构具有六字节prefetch指令流水线。作为执行单元正在执行的当前指令，总线接口单元在从存储器提前读取多达六个字节运算codeS的

Note: Instruction Queue - The 8086 architecture has a six-byte prefetch instruction pipeline. As the Execution Unit is executing the current instruction, the bus interface unit reads up to six bytes of opcodes in advance from the memory.

推荐答案

您是不是你所说的指令队列什么很清楚。

You aren't very clear about what you mean by "instruction queue".

一个意思可能是prefetched说明。在实践中，处理器推测性预读从最后的完成的指令，如下分支或不基于各种类型的分支prediction算法的点的指令流。由于这些的读取的，如果处理器决定放弃另一个（例如，中断例程）当前指令流，它简单地忽略它的预读。

One meaning might be "prefetched instructions". In practice, the processor has speculatively read-ahead in the instruction stream from the point of the last completed instruction, following branches or not based on various types of branch prediction algorithms. Since these are reads, if the processor decides to abandon the current instruction "stream" for another (e.g., the interrupt routine), it simply ignores its read-ahead.

另一个意思可能是指令部分执行的（在飞行/在'管道'），它经常与超标量CPU的情况。在一个异步中断的情况下，处理器必须完成那些受影响系统的可见状态（例如，已致力于一寄存器或存储器的写），并可以或可以不完全依赖于的率性其他指令特定处理器的设计师。在同步陷阱的情况下，处理器来完成，影响状态的说明，而只是放弃休息（OP的短语是零排队，这有正确的概念，但错误的措辞）。

Another meaning might be "instructions partly executed (in flight/in the 'pipeline')", which frequently happens with super-scalar CPUs. In the case of an asynchronous interrupt, the processor must complete those that have affected the visible state of the system (e.g, has committed a write to a register or memory), and may or may not complete other instructions depending on the whims of the specific processor's designers. In the case of a synchronous trap, the processor has to complete instructions that affected state, but simply abandons the rest (OP's phrase was "zeros the queue" which has the right concept but the wrong phrasing).

[添加在OP的要求评论我做了]：
你说8086有一个6字节prefetch指令流水线（坏词恕我直言）。可能有过一个与该属性，但是这是实施的细节，也没有充分的理由相信这是所有8086s的属性。对于现代的CPU，指令prefetch的实现方式是简单地依赖于设计师的聪明。所有你能合理predict是会有一些prefetch方案，这将是你很难发现它的presence在应用程序中，除了关于自我修改对性能的影响和有趣的规则code。

[Adding at OP's request a comment I made]: You say the 8086 has a 6 byte prefetch "instruction pipeline" (bad term IMHO). There may have been one with that property, but that's a detail of the implementation and there's no good reason to believe this is a property of all 8086s. For modern CPUs, the way the instruction prefetch is implemented is simply dependent on the cleverness of the designers. About all you can reasonably predict is there will be some prefetch scheme, and it will be difficult for you to detect its presence in your application program except for impact on performance and funny rules about self-modifying code.

[OP回答的第二个问题]
的其次，我们需要手动处理的IP（如，将其推到在中断堆栈），或在不中断服务例程处理这对我们？的

[Answering OP's second question]: Secondly, do we need to manually handle the IP (like, push it onto the stack upon interrupt) or does the interrupt-service-routine handles this for us?

对于任何类型的陷阱或中断，这足以存储体系结构定义的状态（以下简称登记册，PC等）。对于许多处理器，它是足够的硬件以存储体系结构状态的临界子集，并且让中断程序存储（并最终恢复）的其余部分。因此，对于存储整个国家的责任硬件和软件（保存在硬件实现的努力）。

For any type of trap or interrupt, it is sufficient to store the architecturally defined state (the "registers", PC, etc.). For many processors, it is sufficient for the hardware to store a critical subset of the architectural state, and let the interrupt routine store (and eventually restore) the rest. So the responsibility for storing the entire state is split between hardware and software (to save implementation effort in the hardware).

有关x86家族，通常指令指针（IP）和标志寄存器由硬件压入当前堆栈，控制转移到该中断，并且在中断程序具有通常存储寄存器中的其余指令一个操作系统定义的数据结构通常被称为上下文块。中断例程都做了工作，要么控制返回给应用程序通过重新加载寄存器，然后通过使用特殊的IRET指令重装IP和标志，或者把控制权交给它选择运行一些其他活动的OS调度器，最终使用保存上下文块内容，以重新启动应用程序。

For the x86 family, typically the instruction pointer (IP) and the flags register are pushed by the hardware onto the current stack, control transfers to the interrupt, and the interrupt routine has instructions that store the rest of the registers typically in an operating-system defined data structure often called a "context block". The interrupt routine does its job, and either returns control to the application by reloading the registers, and then reloading the IP and flags by using a special IRET instruction, or it transfers control to an OS scheduler which chooses to run some other activity, eventually using the saved context block content to restart the application.

一个的真正的快速中断例程可能只保存足够的寄存器来完成其重要的工作，然后返回到interruptee前恢复这些寄存器。

A really fast interrupt routine might save just enough registers to do its critical work, and then restore those registers before returning to the interruptee.

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