我如何使用LOCK ASM preFIX阅读价值？ [英] How do I use the LOCK ASM prefix to read a value?

问题描述

我知道如何使用锁，以线程安全的递增值：

I know how to use LOCK to thread-safely increment a value:

  lock inc     [J];

但我怎么读一个线程安全的方式[J]（或任何价值）？该LOCK preFIX不能用MOV使用。如果我做到以下几点：

But how do I read [J] (or any value) in a thread-safe manner? The LOCK prefix can't be used with mov. And if I do the following:

  xor eax, eax;
  lock add eax, [J];
  mov [JC], eax;

这会引发错误就行2。

It raises an error on line 2.

推荐答案

使用 XADD 或MOV指令，而不是加法指令！
参见<一个href=\"http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedprojects/reference_olh/mergedprojects/instructions/instruct32_hh/vc172.htm\">MFENCE, <一href=\"http://www.google.si/webhp?sourceid=chrome#hl=sl&q=LFENCE+intel&aq=f&aqi=&aql=&oq=&gs_rfai=&fp=6aa9248bed43b54b\">LFENCE和<一个href=\"http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedprojects/reference_olh/mergedProjects/instructions/instruct32_hh/vc287.htm\">SFENCE说明！

Use XADD or MOV instruction instead ADD instruction! See also MFENCE, LFENCE and SFENCE instructions!

编辑：
你不能使用ADD指令锁定指令，如果源操作数是内存操作！

You can't use LOCK instruction with ADD instruction if source operand is a memory operand!

从：英特尔®64和IA-32 ArchitecturesSoftware开发者手册

From: "Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual"

在LOCK preFIX只能ppended $ P $
  以下说明，只
  这些形式的说明
  其中目标操作数是
  内存操作数：ADD，ADC，AND，BTC，
  BTR，BTS，CMPXCHG，CMPXCH8B，DEC，INC，
  NEG，NOT，OR，SBB，SUB，XOR，XADD和
  XCHG。如果锁preFIX用于与
  这些指令和
  源操作数是内存操作数，
  未定义操作code异常（#UD）可
  产生。未定义操作code
  异常也会产生如
  在LOCK preFIX用于与任何
  不在上述名单的指令。该
  XCHG指令总是断言
  不管在LOCK＃信号
  presence与否LOCK preFIX的

The LOCK prefix can be prepended only to the following instructions and only to those forms of the instructions where the destination operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If the LOCK prefix is used with one of these instructions and the source operand is a memory operand, an undefined opcode exception (#UD) may be generated. An undefined opcode exception will also be generated if the LOCK prefix is used with any instruction not in the above list. The XCHG instruction always asserts the LOCK# signal regardless of the presence or absence of the LOCK prefix

EDIT2：
形态：英特尔®64和IA-32 ArchitecturesSoftware开发者手册，Volume3A

Form: "Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume3A"

8.1.1保证原子操作。
  英特尔486处理器（以及更高
  因为处理器）保证了
  以下基本内存操作将
  始终原子进行：

8.1.1 Guaranteed Atomic Operations. The Intel486 processor (and newer processors since) guarantees that the following basic memory operations will always be carried out atomically:

  
• 读取或写入字节

  
• 读取或写入字对齐
    在16位边界

  
• 读取或写入一个32位的边界上对齐的双字

  

奔腾处理器（和更新
  因为处理器）保证了
  以下额外的内存操作
  将始终原子进行：

The Pentium processor (and newer processors since) guarantees that the following additional memory operations will always be carried out atomically:

  
• 读取或写入一个64位的边界上对齐四字

  
• 6位访问以适合一个32位之内的非高速缓存存储器位置搜索
    数据总线的P6系列处理器结果
    （和更新的处理器以来）结果
    保证下列结果
    额外的内存操作将结果
    始终原子进行：

  
• 未对齐的16位，32位和64位访问缓存的内存适合结果
    缓存行内

  

访问到高速缓存内存是
  跨总线宽度，高速缓存行拆分，
  和页面的边界，不能保证
  通过英特尔Core 2 Duo是原子，
  英特尔酷睿双核，奔腾M，奔腾4，
  英特尔至强，P6系列，Pentium和
  英特尔486处理器。英特尔酷睿2
  双核，英特尔酷睿双核，奔腾M，
  奔腾4，英特尔至强和P6系列
  处理器提供了总线控制信号
  该许可证外部存储器子系统
  使分裂原子访问;
  然而，不结盟的数据访问的意愿
  严重影响性能
  处理器和应当避免。

Accesses to cacheable memory that are split across bus widths, cache lines, and page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that permit external memory subsystems to make split accesses atomic; however, nonaligned data accesses will seriously impact the performance of the processor and should be avoided.

所以，我读prefare使用<一个href=\"http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedprojects/reference_olh/mergedprojects/instructions/instruct64_hh/6400165.htm\">CMPXCHG用LOCK preFIX指令，如：

So, for reading I prefare to use CMPXCHG instruction with LOCK prefix, like:

LOCK        CMPXCHG   EAX, [J]

有关书面方式：

MOV   [J], EAX
SFENSE

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