指令的数量相当于 [英] equivalent number of instruction

问题描述

我有一个问题（就像我）......

I've a question (just like me)...

但是...如果我写在C或C ++或任何code你想要一个选定的算法...固定的编译器我能确定的指令，但这些说明资讯的数量是不同的对方：X添加，Y MUL，Z MOV，女FADD，T FMUL（F代表浮动）...是否有允许写的等效指令的数量的指令数来比较不同algorith方法或公式还是其他什么东西？有没有你认为有人使用这种类型的指标？它是一个垃圾？

but...if I've a choosen algorithm written in C or C++ or whatever code you want...fixed a compiler I can determine the number of instructions but these intructions are different each other: x ADD, y MUL, z MOV, f FADD, t FMUL (F stands for FLOATING)...Is there a methodology or equation or something else that permits to write the number of instructions in number of "Equivalent instruction" to compare different algorith? Is there somebody of you that use this type of metric? is it a rubbish?

感谢

马可波罗

第2部分：
我知道这dipends上和建筑一般。我的问题是：要确定对软核的不同结构不同的实现算法的执行时间。在y轴上我必须写的时候，X轴指令的数量和图形的点是由建筑的类型参数化（原谅我的英文）。但在X axix我觉得这是更好地使用类似的等价指令号...

Part2: I Know that it dipends on uP and architecture in general. My problem is: To determine a execution time of different algorithms implemented on different architectures of soft core. On y-axis I must write time, on x-axis the number of instruction and the point of the graph are parametrized by the type of architecture (excuse me for my english). But on x-axix I think it's better to use something like number of "equivalent instruction"...

这是个垃圾想法？

推荐答案

您不太了解的问题。执行速度不仅取决于指令，但在指令间的依赖关系也。微处理器可以在给定的这个指令不互相依赖，同时执行多个指令。同时执行多个指令的能力从一个处理器家族的不同而不同。这就是为什么这个任务是真的硬件特有的，它不能被一次解决，所有

You don't quite understand the problem. Execution speed depends not only on instructions but on inter-instruction dependencies also. Microprocessors can execute several instructions at the same time given this instructions don't depend on each other. The ability to execute several instructions at a time differs from one processor family to another. That's why this task is really hardware-specific, it can't be solved once and for all.

所有你能做的就是指令和处理器周期图的执行时间表。处理器周期可能是y轴，指示可以是x轴。你有问题predicting缓存成功和失败与许多指令执行时间将根据缓存命中/未命中相差很大。准备花很多时间与处理器手册。

All you can do is graph an execution timeline of instructions and processor cycles. Processor cycles could be y-axis, instructions could be x-axis. You'll have problems predicting cache hits and misses and execution time of many instructions will vary greatly depending on cache hits/misses. Be ready to spend a lot of time with processors manuals.

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