内存屏障和缓存刷新 [英] memory barrier and cache flush
问题描述
是否存在这样一种内存屏障，即使缓存刷新实现的任何archs？我读到内存屏障只影响CPU的重新排序，但我看了相关的内存屏障语句：确保所有的CPU将看到价值... 的，但对我来说意味着缓存刷新/无效
Is there any archs where a memory barrier is implemented even with a cache flush? I read that memory barrier affects only CPU reordering but I read statements related to the memory barriers: ensures all the cpu will see the value..., but for me it means a cache flush/invalidation.
推荐答案
在pretty多所有现代架构，高速缓存（如L1和L2缓存）是保证硬件一致。没有必要以刷新任何高速缓存以使存储器可见到其它CPU
On pretty much all modern architectures, caches (like the L1 and L2 caches) are ensured coherent by hardware. There is no need to flush any cache to make memory visible to other CPUs.
一个可以假设想象，没有缓存在硬件统一的系统，但它不会像她那样运行操作系统，如Windows和Linux在当前系统中任何事情。
One could imagine hypothetically a system that was not cache coherent in hardware, but it wouldn't look anything like the current systems that run operating systems like Windows and Linux.
内存屏障做三件事情：
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CPU可以pre-获取该公司通过在另一个核心的写入无效读取。这必须是pvented $ P $。 （虽然在x86，这是在硬件pvented $ P $该$ P $对 - 取被锁定到L1高速缓冲存储器行，所以，如果其它CPU无效的高速缓存线时，$ P $对 - 取被无效，以及。 ）
The CPU may pre-fetch a read that's invalidated by a write on another core. This must be prevented. (Though on x86, this is prevented in hardware. The pre-fetch is locked to the L1 cache line, so if another CPU invalidates the cache line, the pre-fetch is invalidated as well.)
CPU可能邮报写道，而不是把他们在其L1缓存呢。这些写入操作必须完成至少L1缓存。
The CPU may "post" writes and not put them in its L1 cache yet. These writes must be completed at least to L1 cache.
CPU可以重新排序读取和对存储器屏障的一侧写入与读取和在另一侧写入。取决于存储器屏障的类型，其中一些重新排序的必须被禁止。 （例如，读X;读出用Y; 不保证读取顺序发生，但阅读X;。memory_barrier（）;读出用Y ; 通常执行）
The CPU may re-order reads and writes on one side of the memory barrier with reads and writes on the other side. Depending on the type of memory barrier, some of these re-orderings must be prohibited. (For example, read x; read y; doesn't ensure the reads happen in that order. But read x; memory_barrier(); read y; typically does.)
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