在x86竞争条件 [英] Race condition on x86

问题描述

有人能解释一下这句话：

Could someone explain this statement:

shared variables
x = 0, y = 0

Core 1       Core 2
x = 1;       y = 1;
r1 = y;      r2 = x;

这怎么可能有 R1 == 0 和 R2 == 0 x86处理器？

巴尔托什卢斯基并发性的语言。

推荐答案

这个问题可能会出现由于涉及的指令重新排序的。换句话说，两个处理器可以将 R1 和 R2 之前分配变量 X 和是，如果他们发现这样会产生更好的性能。这可以通过添加存储器屏障时，这会强制排序约束来解决。

The problem can arise due to optimizations involving reordering of instructions. In other words, both processors can assign r1 and r2 before assigning variables x and y, if they find that this would yield better performance. This can be solved by adding a memory barrier, which would enforce the ordering constraint.

要引用幻灯片您在您的文章中提到：

To quote the slideshow you mentioned in your post:

现代多核/语言破解顺序一致性

对于x86架构，读最好的资源是英特尔®64和IA -32架构软件开发人员手册（章 8.2内存排序）。第8.2.1节和第8.2.2节描述了实现的存储器排序
英特尔486，奔腾，英特尔酷睿2双核，英特尔凌动，英特尔酷睿双核，奔腾4，英特尔
Xeon和P6系列处理器：名为处理器顺序内存模型，而不是程序排序（强排序）上了年纪英特尔386架构（其中，读取和写入指令的顺序总是签发的指令流中出现）。

Regarding the x86 architecture, the best resource to read is Intel® 64 and IA-32 Architectures Software Developer’s Manual (Chapter 8.2 Memory Ordering). Sections 8.2.1 and 8.2.2 describe the memory-ordering implemented by Intel486, Pentium, Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, Intel Xeon, and P6 family processors: a memory model called processor ordering, as opposed to program ordering (strong ordering) of the older Intel386 architecture (where read and write instructions were always issued in the order they appeared in the instruction stream).

本手册介绍了处理器订货内存模型的许多排序保证（如负载不与其他负载重新排序的店铺不与其他商店重新排序的店铺不与旧负荷的等）重新排序，但它也说明允许的重新排序规则，这将导致竞争条件在OP的帖子：

The manual describes many ordering guarantees of the processor ordering memory model (such as Loads are not reordered with other loads, Stores are not reordered with other stores, Stores are not reordered with older loads etc.), but it also describes the allowed reordering rule which causes the race condition in the OP's post:

8.2.3.4负荷可能会重新排序与此前存储于不同的
  位置

在另一方面，如果指令的原来顺序被交换：

On the other hand, if the original order of the instructions was switched:

shared variables
x = 0, y = 0

Core 1       Core 2
r1 = y;      r2 = x;
x = 1;       y = 1;

在这种情况下，处理器确保了 R1 = 1 和 R2 = 1 的情况是不允许的（因的 8.2.3.3商店并不是重新排序随着此前负载的担保），这意味着这些指令绝不会在各个内核进行重新排序。

In this case, processor guarantees that r1 = 1 and r2 = 1 situation is not allowed (due to 8.2.3.3 Stores Are Not Reordered With Earlier Load guarantee), meaning that those instructions would never be reordered in individual cores.

要与不同的架构比较这，看看这篇文章：内存排序现代微处理器（这一形象明确）。你可以看到，基于Itanium（IA-64）也更重排序比IA-32架构。

To compare this with different architectures, check out this article: Memory Ordering in Modern Microprocessors (this image specifically). You can see that Itanium (IA-64) does even more reordering than the IA-32 architecture.

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