为什么不能OS使用全64位寻址？为什么只有48位？ [英] Why can't OS use entire 64-bits for addressing? Why only the 48-bits?

问题描述

我在读理解Linux内核。

  

分页的64位架构

     

正如我们已经看到在previous   段，两级寻呼是常用   所使用的32位微处理器。   两级寻呼，然而，这不是   适合于采用电脑   64位架构。让我们用一个   思想实验来解释为什么：

     

首先，假设一个标准的页面大小   4 KB。由于1 KB的覆盖范围   2 ¹⁰ 地址，4 KB占地面积2 ¹²   地址，因此偏移字段是12   位。这使得高达52比特的   线性地址要分发   表和目录之间   域。 如果我们现在决定使用   只有48的64位用于寻址   （此限制给我们留下了一个   舒适的256 TB的地址空间！）的   其余48-12 = 36位将   已被表之间的分裂   目录域。如果我们现在决定   保留18比特用于每这两个   字段，这两个页面目录和   每个进程的页表应   包括2 ¹⁸ 项即，超过   256,000项。

1. 如果我们现在决定只的64位48用于解决。为什么？ ＆放大器;为什么只有48位？为什么不是其他数字？

2. 嗯，我只是一个普通PC用户的放大器;程序员。它只是很难相信对我说，32位寻址，即4GB（2GB / 3GB更正确的）每个进程的地址空间是有限的。如果你的真正的遇到了这个限制。请给我的例子。

3. 这是什么限制窗口？

4. 我知道，虚拟内存=物理内存和放！;处理器地址引脚无关虚拟内存。这是一个完全不同的问题。如何知道的地址管脚的数目（=地址总线的大小）的处理器。 http://ark.intel.com 处理器规格不包括该规范。

答：

请参阅<一href="http://stackoverflow.com/questions/3219562/why-cant-os-use-entire-64-bits-for-addressing-why-only-the-48-bits/3220642#3220642">Paul贝茨的回答为第一个问题合理的答案。

解决方案

  

如果我们现在决定只的64位48用于解决。为什么？ ＆放大器;为什么只有48bits？为什么不是其他数字？

系统架构师做出权衡。 256TB似乎是绰绰有余的空间1进程的地址空间。记住虚拟地址！=物理地址，并且通常来说，每个进程具有其自己的地址空间

只要指针是64位，这更多的是执行能力问题比什么都重要。如果和放大器;当48位变成一个限制，则OS可被调整，以使用64位地址空间的更多位而不破坏应用程序不兼容。现在，建筑师只是买自己的时间很舒服的金额。

这可能都与处理器端的虚拟寻址能力，尽可能多的处理器现在有存储器管理单元来处理虚拟 - >物理内存映射

  

如何知道的地址管脚的数目（=地址总线的大小）的处理器。 http://ark.intel.com 处理器规格不包括该规范。

这是在大多数情况下不相关的。这是一种方法，一个处理器来实现各种物理寻址方案。一个64位处理器，可以实现外部地址/数据总线，用于其完整的地址空间，64，32，16，8，4，2，或1地址引脚当总线同步和地址位都将在时间上多路复用。此外，虚拟地址=物理地址！; 64位虚拟寻址可与48位或32位的物理地址来实现（只是你将限于2 ⁴⁸ 或2 ^{的存储器32功能}字）。

更新：如果您真的想知道，你得看问题每个处理器的数据表。例如。 英特尔酷睿2 - 关于信号的数据表会谈第4.2节 - 地址总线是36位宽（但确实是33条信号线;数据宽度为64位= 8字节，以便其他3条线可能不必要与正确的数据对齐）

  

嗯，我只是一个普通PC用户的放大器;程序员。它只是很难相信对我说，32位寻址，即.. 4GB（2GB / 3GB更正确）处理每个进程的空间是有限的。如果你真的遇到了这个限制。请给我的例子。

两个词： 内存映射文件 的

I'm reading "Understanding Linux Kernel".

Paging for 64-bit Architectures

As we have seen in the previous sections, two-level paging is commonly used by 32-bit microprocessors. Two-level paging, however, is not suitable for computers that adopt a 64-bit architecture. Let's use a thought experiment to explain why:

Start by assuming a standard page size of 4 KB. Because 1 KB covers a range of 2¹⁰ addresses, 4 KB covers 2¹² addresses, so the Offset field is 12 bits. This leaves up to 52 bits of the linear address to be distributed between the Table and the Directory fields. If we now decide to use only 48 of the 64 bits for addressing (this restriction leaves us with a comfortable 256 TB address space!), the remaining 48-12 = 36 bits will have to be split among Table and the Directory fields. If we now decide to reserve 18 bits for each of these two fields, both the Page Directory and the Page Tables of each process should include 2¹⁸ entries that is, more than 256,000 entries.

1. "If we now decide to use only 48 of the 64 bits for addressing". Why? & Why only 48 bits? Why not some other number?

2. Well, I'm just a regular PC user & programmer. Its just hard to believe for me that 32-bit addressing i.e. 4GB (2GB/3GB to be more correct) address space per process is a limit. If you really encountered this limit. Please give me example.

3. What is this limit for windows?

4. I know that virtual memory != physical memory & processor address pins have nothing to do with virtual memory. This is a completely different question. How to know the number of address pins (= size of address bus) for a processor. http://ark.intel.com specifications of a processor doesn't include this spec.

Answer:

See Paul Betts's answer for reasonable answer for 1st question.

解决方案

"If we now decide to use only 48 of the 64 bits for addressing". Why? & Why only 48bits? Why not some other number?

System architects make tradeoffs. 256TB seems like more than enough room for 1 process's address space. Remember virtual address != physical address, and generally speaking, each process has its own address space.

As long as pointers are 64 bits, this is more of a performance capability issue than anything else. If & when 48 bits becomes a limitation, the OS could be tweaked to use more bits of the 64-bit address space without breaking application incompatibility. For now, the architects are just buying themselves a very comfortable amount of time.

It may have to do with processor-side virtual addressing capabilities, as many processors now have memory management units to handle the virtual -> physical memory mapping.

How to know the number of address pins (= size of address bus) for a processor. http://ark.intel.com specifications of a processor doesn't include this spec.

This is for the most part irrelevant. It's a way for a processor to implement various physical addressing schemes. A 64-bit processor could achieve external address/data buses for its complete address space with 64, 32, 16, 8, 4, 2, or 1 address pin if the bus is synchronous and the address bits get multiplexed in time. Again, virtual address != physical address; 64-bit virtual addressing could be implemented with 48-bit or 32-bit physical addresses (just that you would be limited to 2⁴⁸ or 2³² words of memory).

update: if you really want to know, you have to look at the datasheet of each processor in question. E.g. Intel Core 2 Duo -- section 4.2 of the datasheet talks about the signals -- the address bus is 36-bits wide (but is really 33 signal lines; the data width is 64-bit = 8 bytes so the other 3 lines are probably unnecessary with proper data alignment)

Well, I'm just a regular PC user & programmer. Its just hard to believe for me that 32-bit addressing ie.. 4GB (2GB/3GB to be more correct) address space per process is a limit. If you really encountered this limit. Please give me example.

Two words: memory-mapped files.

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