L1和L2缓存的行大小 [英] Line size of L1 and L2 caches

问题描述

在此论坛上的上一个问题据了解，在大多数存储系统中，L1缓存是L2缓存的子集，这意味着从L2删除的所有条目也将从L1删除.

From a previous question on this forum, I learned that in most of the memory systems, L1 cache is a subset of the L2 cache means any entry removed from L2 is also removed from L1.

所以现在我的问题是我如何确定L1高速缓存中对应于L2高速缓存中的条目的条目. L2条目中存储的唯一信息是标签信息.基于此标签信息，如果L1和L2缓存的行大小不同，则如果我重新创建addr，它可能会跨越L1缓存中的多行.

So now my question is how do I determine a corresponding entry in L1 cache for an entry in the L2 cache. The only information stored in the L2 entry is the tag information. Based on this tag information, if I re-create the addr it may span multiple lines in the L1 cache if the line-sizes of L1 and L2 cache are not same.

该体系结构是否真的困扰于刷新这两条线，或者只是保持L1和L2高速缓存具有相同的线大小.

Does the architecture really bother about flushing both the lines or it just maintains L1 and L2 cache with the same line-size.

我了解这是一项政策决策，但我想了解常用的技术.

I understand that this is a policy decision but I want to know the commonly used technique.

推荐答案

在核心i7中，L1，L2和L3中的行大小相同:即64字节. 我想这会简化维护包容性和一致性的过程.

In core i7 the line sizes in L1 , L2 and L3 are the same: that is 64 Bytes. I guess this simplifies maintaining the inclusive property, and coherence.

请参阅第10页， https://www.aristeia.com/TalkNotes/ACCU2011_CPUCaches.pdf

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