在L2逐出时从L1缓存中逐出缓存 [英] Cache eviction from L1 cache on L2 eviction
问题描述
我对存储系统遵循的策略有一个基本问题。
I have a basic question about the policy followed by the memory system.
考虑一个具有私有L1和L2缓存的内核。在二级高速缓存之后，我们有了一条总线，在该总线上运行一致性通信。现在，如果从L2缓存中逐出了地址（X）的缓存行，是否有必要从L1缓存中逐出该地址？
Consider a core with private L1 and L2 caches. After L2 cache we have a bus on which the coherence traffic runs. Now, if a cache line for address(X) is evicted from the L2 cache, is it necessary to evict that address from the L1 cache ??
驱逐的原因可能是因为它有助于保持一致性协议的不变性（如果l2中的一行显示无效，则该核心不包含该地址）。
The reason for eviction can be that it helps in maintaining the invariant of the coherence protocol [if a line in l2 shows invalid this core does not contain this address].
推荐答案
有三种不同的设计，并且全部使用。
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独占：L1缓存中的数据永远不在L2缓存中。 L2高速缓存中的数据永远不会在L1高速缓存中。
Exclusive: Data in the L1 cache is never in the L2 cache. Data in the L2 cache is never in the L1 cache.
包含在内：L1高速缓存中的数据也必须位于L2高速缓存中。
Inclusive: Data in the L1 cache must also be in the L2 cache.
都不：L1高速缓存中的数据可能会或可能不会在L2高速缓存中。
Neither: Data in the L1 cache may or may not be in the L2 cache.
每个都有优点和缺点。包含方案允许缓存一致性协议忽略L1缓存-如果数据不在L2缓存中，则数据不在L1缓存中。
Each of these has advantages and disadvantages. The inclusive scheme allows the cache coherency protocol to ignore the L1 cache -- if data isn't in the L2 cache, it isn't in the L1 cache. But the exclusive scheme makes the most effective use of precious cache memory.
包容性设计正变得越来越流行，因为更快的内核间同步变得比具有稍微更大的有效容量更重要。缓存大小。
Inclusive designs are becoming more popular because faster inter-core synchronization is becoming more important than having slightly larger effective cache sizes.
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