如何在Verilog中声明输入和输出类型 [英] How to declare input and output types in verilog
问题描述
我有一个实例化两个模块的顶级模块:
fillRam fillRam1(
.clk(mclk),
.ramaddrb(ramaddrb),
.romaddrb(romaddrb),
.romoutb(romoutbwire),
.raminb(raminb));
vga vgainst(
.ck(mclk),
.HS(HS),
.VS(VS),
.outRed(OutRed),
.outGreen(OutGreen),
.outBlue(OutBlue),
.sw(sw),
.romouta(romoutawire),
.ramouta(ramoutawire),
.romaddra(romaddra),
.ramaddra(ramaddra));
在此顶部模块中，我还有两个模块用于在RAM和ROM上建立连接.
rom rom_instance (
.clka(mclk), // input clka
.addra(romaddrawire), // input [14 : 0] addra
.douta(romouta), // output [7 : 0] douta
.clkb(ck), // input clkb
.addrb(romaddrbwire), // input [14 : 0] addrb
.doutb(romoutb) // output [7 : 0] doutb
);
我要做的是从vga模块获取romaddra值，将其提供给rom_instance，然后获取romouta值，并将其返回给vga模块. 为此，我声明了两个变量:
reg [14:0] romaddra;
wire [14:0] romaddrawire;
reg [7:0] romouta;
wire [7:0] romoutawire;
assign romaddrawire = romaddra;
assign romoutawire = romouta;
在每个时钟周期中，我从vga实例获取romaddra值，将其写入romaddrawire并将其提供给ROM实例.然后，我取romouta值，将其写入romoutawire，然后将其返回给VGA实例.
我在其他rom端口和ram端口上也有类似的声明.但在所有这些中，我都会遇到此错误.
ERROR:HDLCompilers:102 - "top.v" line 82 Connection to output port 'romaddra' must be a net lvalue
在vga verilog代码中:
output reg [14:0] romaddra;
和rom verilog中:
output [7 : 0] douta;
我对整个reg和电线类型感到非常困惑.如果有人能解释这里出了什么问题以及原因，我将非常高兴.谢谢.
如果您的工作流程允许您使用SystemVerilog，则所有这些内容都将变为logic而不是reg或wire，并且您的问题就消失了. >
您可以稍后阅读更多内容，但现在使用wire进行连接或作为Assign语句的一部分.要在always块中定义值时，请使用reg:
wire a_wire;
wire b_wire;
example_a_module(
.a( a_wire )
);
example_b_module(
.a( a_wire )
);
assign b_wire = ~a_wire ;
Regs
reg a_reg;
reg b_reg;
always @* begin
a_reg = something_else;
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
b_reg <= 1'b0;
end
else begin
b_reg <= something_else;
end
end
如果您按名称(看起来像您自己)而不是按顺序进行连接，则输出端口可以是任何类型.
输出a是导线类型:
module example_a_module(
output a
);
endmodule
这里b是10位的reg类型:
module example_c_module(
output reg [9:0] b
);
endmodule
I have this top module that instantiate two modules:
fillRam fillRam1(
.clk(mclk),
.ramaddrb(ramaddrb),
.romaddrb(romaddrb),
.romoutb(romoutbwire),
.raminb(raminb));
vga vgainst(
.ck(mclk),
.HS(HS),
.VS(VS),
.outRed(OutRed),
.outGreen(OutGreen),
.outBlue(OutBlue),
.sw(sw),
.romouta(romoutawire),
.ramouta(ramoutawire),
.romaddra(romaddra),
.ramaddra(ramaddra));
In this top module, i also have two module that makes the connections on the RAM and ROM.
rom rom_instance (
.clka(mclk), // input clka
.addra(romaddrawire), // input [14 : 0] addra
.douta(romouta), // output [7 : 0] douta
.clkb(ck), // input clkb
.addrb(romaddrbwire), // input [14 : 0] addrb
.doutb(romoutb) // output [7 : 0] doutb
);
The thing i want to do is, get the romaddra value from vga module, give it to rom_instance, and get the romouta value and give it back to vga module back. I declare two variables for that:
reg [14:0] romaddra;
wire [14:0] romaddrawire;
reg [7:0] romouta;
wire [7:0] romoutawire;
assign romaddrawire = romaddra;
assign romoutawire = romouta;
In every clock cycle, i get the romaddra value from vga instance, write it to romaddrawire and give it to the ROM instance. Then i take the romouta value, write it to romoutawire and give it back to the VGA instance.
I have similar declarations on other rom ports and ram ports. But in all of them i get this error.
ERROR:HDLCompilers:102 - "top.v" line 82 Connection to output port 'romaddra' must be a net lvalue
in vga verilog code:
output reg [14:0] romaddra;
and in rom verilog:
output [7 : 0] douta;
Im very confused about this whole reg and wire types. I would be glad if someone explain what is going wrong here and the reason aswell. Thanks.
If your workflow allows you to use SystemVerilog then these can all become logic instead of reg or wire and your problem goes away.
You can read up more on it later but for now use a wire for connectivity or as part of an assign statement. Use reg when you want to define the value in an always block:
wire a_wire;
wire b_wire;
example_a_module(
.a( a_wire )
);
example_b_module(
.a( a_wire )
);
assign b_wire = ~a_wire ;
Regs
reg a_reg;
reg b_reg;
always @* begin
a_reg = something_else;
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
b_reg <= 1'b0;
end
else begin
b_reg <= something_else;
end
end
Output ports can be any type, if you hook them up by name (it looks like you have) rather than by order.
Output a is a wire type:
module example_a_module(
output a
);
endmodule
Here b is a 10 bit reg type:
module example_c_module(
output reg [9:0] b
);
endmodule
这篇关于如何在Verilog中声明输入和输出类型的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
