VHDL STD_LOGIC_VECTOR通配符值 [英] VHDL STD_LOGIC_VECTOR Wildcard Values

问题描述

我一直在尝试用VHDL代码为我在Altera DE1板上实现的简单16位处理器编写有限状态机.在有限状态机中，我有一个CASE语句，用于处理不同的16位指令，这些指令由16位STD_LOGIC_VECTOR带到FSM中.但是，在有限状态机对指令进行解码的解码状态下，我遇到了一些麻烦.指令之一是ADD，它将两个寄存器作为操作数，第三个作为目标寄存器.但是，我还有一条ADD指令，该指令将一个寄存器和一个5位立即数作为操作数，并使用第二个寄存器作为目标地址.我的问题是，在CASE语句中，我需要能够区分两个不同的ADD指令.因此，我认为，如果在CASE语句中使用通配符值(例如-"或"X")，则仅用两种情况就可以区分两者，而不必列出所有可能的寄存器/立即值组合.例如:

I've been trying to write a Finite State Machine in VHDL code for a simple 16-bit processor I'm implementing on an Altera DE1 board. In the Finite State Machine, I have a CASE statement that handles the different 16-bit instructions, which are brought into the FSM by a 16-bit STD_LOGIC_VECTOR. However, I'm having a little trouble in the decode state where the Finite State Machine decodes the instruction. One of the instructions is an ADD which takes two registers as operands and a third as the destination register. However, I also have an ADD instruction which takes a register and a 5-bit immediate value as operands and a second register for the destination. My problem is that in the CASE statement, I need to be able to differentiate between the two different ADD instructions. So, I thought that if I use wildcard values like "-" or "X" in the CASE statement, I would be able to differentiate between the two with just two cases instead of listing all of the possible register/immediate value combinations. For example:

    CASE IR IS --(IR stands for "Instruction Register")
      WHEN "0001------0-----" => (Go to 3-register add);
      WHEN "0001------1-----" => (Go to 2-register/immediate value add);
      WHEN OTHERS => (Do whatever);
    END CASE;

这些不是我仅有的两个说明，我只是将这两个说明放短了一些.当我编译并运行此代码时，处理器进入解码"状态时将停止执行.此外，Quartus还给出了许多警告，例如"LC3FSM.vhd(37)上的VHDL选择警告:忽略了包含元值"0001 ------ 0 -----""的选择" 我对如何实现这一目标一无所知.我真的不需要，也可能不需要定义每个单一的16位组合，并且我希望有一种方法可以在STD_LOGIC_VECTOR中使用通配符以最小化我必须定义的组合数量.

These aren't the only two instructions I have, I just put these two to make this post a little shorter. When I compile and run this code, the processor stops executing when it gets to the "decode" state. Also, Quartus gives many, many warnings saying things like "VHDL choice warning at LC3FSM.vhd(37): ignored choice containing meta-value ""0001------0-----""" I am at a loss as to how to go about accomplishing this. I REALLY do not and probably don't need to define every single 16-bit combination, and I hope there's a way to use wildcards in a STD_LOGIC_VECTOR to minimize the number of combinations I will have to define.

有人知道如何做到这一点吗?

Does anybody know how to accomplish this?

谢谢

推荐答案

假设您不需要指令中的其他位，则可以通过使用预检查过程掩盖其他位来解决此问题. (或者只是确保在编写指令时将其他位复位?)

Assuming you don't need the other bits in the instruction you could hack your way around this by masking the other bits with a pre-check process. (Or just ensure the other bits are reset when you write the instruction?)

这确实有点hacking.

This really is a bit of a hack.

假设IR存储为变量

if IR(15 downto 12) == "0001" then
    IR := IR_in(15 downto 12) & "0000000" & IR_in(5) & "00000";
else
    IR := IR_in
end if;

CASE IR IS --(IR stands for "Instruction Register")
  WHEN "0001000000000000" => (Go to 3-register add);
  WHEN "0001000000100000" => (Go to 2-register/immediate value add);
  WHEN OTHERS => (Do whatever);
END CASE;

或者，假设您的指令经过了仔细的考虑(前四位是命令字还是沿行的内容?)，您可以进行嵌套的case语句，并根据需要在这些子块中进行区分.

Alternatively assuming your instruction is cleverly thought out (are the first four bits the command word or something along those lines?) you could do nested case statements and do the differentiation as needed in those sub blocks.

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