作为 std_logic_vector 提供的数组地址 [英] Address of array provided as std_logic_vector

问题描述

我正在尝试构建一个 ROM，它具有作为访问地址的声明 a : in std_logic_vector(5 downto 0) .我的问题是我不知道如何使用 std_logic_vector 访问 ROM 数组，我应该使用强制转换为整数还是我还能做什么?

I'm trying to construct a ROM, which has as declaration a : in std_logic_vector(5 downto 0) for the access address. My problem its that I don't know how to access the ROM array with a std_logic_vector, Should I use a cast to integer or what else can I do?

我的代码:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
entity imem is
    GENERIC(CONSTANT N : INTEGER := 32);
    port (a : in std_logic_vector(5 downto 0);
         result : out std_logic_vector(N-1 downto 0));
end imem;


architecture behavior of imem is
    signal addres : integer;
    type memory is array (0 to 64) of std_logic_vector(N-1 downto 0) ;
    constant myrom : memory := (
         2 => x"11111111" , --255
         3 => x"11010101" , 
         4 => x"01101000" , 
         6 => x"10011011" , 
         8 => x"01101101" , 
         9 => x"00110111" , 
         others => x"00000000" ) ;

begin 
    addres <= signed(a);
    result <= memory(addres);

end behavior;

使用如图所示的代码，我收到以下错误:

With this code as shown I get the following error:

imem.vhd:25:21: can't match type conversion with type integer  
imem.vhd:25:21: (location of type conversion)
imem.vhd:26:21: conversion not allowed between not closely related types  
imem.vhd:26:21: can't match type conversion with type array type "std_logic_vector"
imem.vhd:26:21: (location of type conversion)
ghdl: compilation error  

推荐答案

假设 a 是一个无符号地址值，那么你必须先将它转换为无符号，然后再转换为整数.请注意，result 应该访问 myrom 而不是 memory 类型.代码可以是:

Assuming that a is an unsigned address value, then you must first cast it to unsigned, and then to integer. Note that the result should access myrom and not memory type. The code can then be:

addres <= to_integer(unsigned(a));
result <= myrom(addres);

你甚至可以跳过中间的 addres 信号并执行:

And you can even skip the intermediate addres signal and do:

result <= myrom(to_integer(unsigned(a)));

memory 类型也比要求的长 1，因为 6 位 a 输入只能覆盖 0 .. 63，而不是 0 .. 64.声明 memory 类型的更好方法是使用 'length 属性作为 a，例如:

The memory type is also one longer than required, since the 6-bit a input can only cover 0 .. 63, and not 0 .. 64. A better way to declare the memory type would be through use the the 'length attribute for a, like:

type memory is array (0 to 2 ** a'length - 1) of std_logic_vector(N-1 downto 0);

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