VHDL std_logic_vector使用“downto”进行索引。 [英] VHDL std_logic_vector indexing with "downto"

问题描述

我想分别设置std_logic_vector的位，以便轻松设置各个位或位组的注释。这就是我所拥有的：

  signal DataOut：std_logic_vector（7 downto 0）; 
 ... 
 DataOut< =（5 =>'1'， - 指令定义
 4 =>'1'， - 数据长度控制位，高= 8位总线模式选择
 3 =>'1'， - 显示行号ctrl位，高和&n; N3选项引脚到VDD = 3行显示
 2 =>'0'， -  Double高度字体类型控制字节，未选中
 1 downto 0 =>01， - 选择指令表1 
 others =>'0' - 对于位6,7 
） ; 
  

但是，我对downto语句有疑问，使用Xilinx时出现以下错误ISE：

 类型std_ulogic与字符串litteral 
   
 
 
避免使用等值的任何解决方案
  1 =>' 0'，
 0 =>'1'，
  
并允许我设置逐块？
解决方案
作业 X downto Y =>当A是数组的元素时，'A'是正确的。例如，此代码段是正确的：
  1 downto 0 => '1'，
  
此代码段错误：
  1 downto 0 => 01，
  
因此，您的作业是非法的。作为您的代码，您可以指定为：
  DataOut< =（5 downto 3 =>'1'，
 2 downto 1 =>'0'，
 0 =>'1'，
 others =>'0'
）; 
  
如果你想通过数组访问/分配，你可以使用连接：
  DataOut< = Something_0& Something_1& 01; 
  
虽然某事_ * 是 std_logic_vector  
 
I would like to set bits of a std_logic_vector separately in order to easily set comments for individual bits or group of bits. Here is what I have:
signal DataOut : std_logic_vector(7 downto 0);
...
DataOut <= (                        5=>'1',     -- Instruction defined
                                    4=>'1',     -- Data length control bit, high=8bit bus mode selected
                                    3=>'1',     -- Display Line Number ctrl bit, high & N3 option pin to VDD=3 lines display
                                    2=>'0',     -- Double height font type control byte, not selected
                                    1 downto 0=>"01",   -- Select Instruction table1
                                    others=>'0' -- for bits 6,7
                                    );
However, I've a problem with the "downto" statement, I get the following error using Xilinx ISE:
Type std_ulogic does not match with a string litteral
Any solution to avoid  using the equivalent 
1=>'0',
0=>'1',
and to allow me to set bits by block?
解决方案
The assignment X downto Y => 'A' is correct when A is a element of array. For example, this snippet is correct:
1 downto 0 => '1',
And this snippet is wrong:
1 downto 0 => "01",
Therefore, your assignment is illegal. As your code, you can assign as:
DataOut <= (                        5 downto 3 =>'1',     
                                    2 downto 1 =>'0',     
                                    0 => '1',  
                                    others=>'0' 
                                    );
If you want to access/assign by a feild of array, you can use concatenation:
DataOut <= Something_0 & Something_1 & "01";
While Something_* is std_logic_vector

                        
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