字长和数据总线 [英] word size and data bus

问题描述

我对单词大小的定义感到困惑。我读到处理器的字长就是它的数据总线宽度。就像8位处理器一样，它具有8位宽的数据总线。我最近读到虚拟地址空间的最大大小由字大小决定，即，如果字大小为n位，则最大虚拟地址空间为2 ^ n -1。但是我一直认为最大的虚拟地址空间由地址总线宽度决定，即一个n位宽的地址总线最多可以寻址2 ^ n个字节。那么，什么是真的？

I am confused about the definition of word size. I read that the word size of a processor is its data bus width. Like an 8 bit processor has an 8 bit wide data bus. I recently read that the maximum size of the virtual address space is determined by word size i.e. if the word size is n bits the max virtual address space is 2^n -1. But I always thought that maximum virtual address space is determined by address bus width i.e. an n bits wide address bus can address maximum 2^n bytes. So, what is true?

此外，这与指针有关，因为n位数据总线能够仅携带一个n位地址。因此，最多可以通过指针访问2 ^ n个字节。

Also, is this related to pointers as an n bit data bus is capable of carrying only an n bit address. So, maximum 2^n bytes can be accessed via pointers.

推荐答案

我首先要说的是，您可能有些困惑因为几十年前事情变得更简单，而您对术语的理解是基于这些更简单的机器。

I'll first say that some of your confusion probably comes from the fact that things were simpler a few decades ago and your understanding of terms is based on these simpler machines.

字长的定义。我读到处理器的字长就是它的数据总线宽度。就像8位处理器具有8位宽的数据总线一样。

I am confused about the definition of word size.I read that the word size of a processor is its data bus width. Like an 8 bit processor has an 8 bit wide data bus.

绝对不是。数据总线与之完全无关。最好将处理器的字长（从来没有真正精确的术语）最好地定义为算术的最大自然大小，通常是机器中寄存器的大小。这通常是数据路径的宽度（与数据总线明显不同）。数据路径就是ALU的宽度。字长通常与指针长相同。

Definitely not. Data bus with is completely unrelated to this. The word size (which has never really been a precise term) of a processor is best loosely defined as the largest natural size for arithmetic which is generally the size of the registers in the machine. This is quite frequently the width of the data path (which is distinctly different from the data bus). The data path is simply the width of the ALUs. The word size is often the same as the pointer size.

我最近读到虚拟地址空间的最大大小由字决定大小，即如果字大小为n位，则最大虚拟地址空间为2 ^ n -1。但是我一直认为最大的虚拟地址空间由地址总线宽度决定，即一个n位宽的地址总线可以寻址最大2 ^ n个字节。那么，什么是真的？

I recently read that the maximum size of the virtual address space is determined by word size i.e. if the word size is n bits the max virtual address space is 2^n -1. But i always thought that maximum virtual address space is determined by address bus width i.e. an n bits wide address bus can address maximum 2^n bytes. So, what is true?

否。虚拟地址空间的大小仅由页表（和TLB）的虚拟页号中的位数确定。在当前基于amd64的计算机上，仅48位虚拟地址可用。高16位是位47的符号扩展。在当前的amd64机器上，物理地址大小为52位。这些物理地址位是在总线上发送的。尽管总线一词确实是不正确的。几乎所有的链接都是点对点的（DDRx DRAM是一个例外），并且使用打包格式（标头+有效负载）代替地址线和数据线。

No. The size of the virtual address space is simply determined by the number of bits in the virtual page number of the page table (and the TLB). On current amd64 based machines, only 48 bits of the virtual address are useable. The upper 16 are a sign extension of bit 47. On current amd64 machines, the physical address size is 52 bits. These physical address bits are the ones that are sent on the bus. Though even the term bus is really incorrect. Almost all links are point-to-point (DDRx DRAM is an exception) and use a packetized format (header + payload) instead of address wires and data wires.

这也与指针有关，因为n位数据总线只能承载n位地址。因此，最多可以通过指针访问2 ^ n个字节。

Also, is this related to pointers as an n bit data bus is capable of carrying only an n bit address. So, maximum 2^n bytes can be accessed via pointers.

许多（几乎所有偶数）具有单独地址总线的机器，使用比地址位数更窄的地址总线。这些位被简单地拆分并使用多个时钟周期在总线上发送。 DDRx DRAM就是另一个例子。

Many (almost all even) machines that have a separate address bus, use an address bus that is narrower than the the number of address bits. These bits are simply split up and sent across the bus using multiple clock cycles. DDRx DRAM is another example of this.

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