Verilog:“……不是常数"； [英] Verilog: "... is not a constant"

问题描述

我创建了三根电线:

wire [11:0] magnitude;
wire [3:0] bitsEnd;
wire [3:0] leadingBits;

所有这些都使用组合逻辑分配一些表达式.以下代码工作正常:

All of them are assigned some expression using combinational logic. The following code works fine:

assign leadingBits[3] = magnitude[bitsEnd + 3];
assign leadingBits[2] = magnitude[bitsEnd + 2];
assign leadingBits[1] = magnitude[bitsEnd + 1];
assign leadingBits[0] = magnitude[bitsEnd + 0];

但是，以下(看似等效的)代码给出了错误bitsEnd is not a constant:

However, the following (seemingly equivalent) code gives the error bitsEnd is not a constant:

assign leadingBits[3:0] = magnitude[bitsEnd + 3:bitsEnd];

这个作业我可以不使用速记吗?为什么在第二种情况下会出现这个错误而不是第一种情况?

Can I not use shorthand for this assignment? Why would this error be raised in the second case but not the first?

推荐答案

在 Verilog 中，您不能使用变量(即 bitsEnd)作为范围的结束.您可以使用 +:/-: 操作员来解决您的问题:

In Verilog you can't use a variable (i.e. bitsEnd) as the end of range. You can use +:/-: operator to solve your issue:

assign leadingBits = magnitude[bitsEnd+3 -: 4];

在第一种情况下，您只计算单个索引(它不是一个范围).这就是编译器没有抱怨它的原因.

In the first case you only calculate single index (it's not a range). That's why the compiler is not complaining about it.

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